INTEGRATED CIRCUIT MEMORY DEVICE

• US 20120300555A1
• Filed: 05/23/2012
• Published: 11/29/2012
• Est. Priority Date: 05/27/2011
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: CHOI, Joo-Sun, SHIN, Choong-Sun
• Granted Patent: US 8,817,549 B2
• Time in Patent Office: Days
• US Class Current: 365/189.03
• CPC Class Codes: G11C 11/408 Address circuits
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A semiconductor memory device includes a plurality of memory regions formed on one chip, each of the memory regions having a plurality of volatile memory cells that are formed with a density or capacity of 2̂K bits, where K is an integer greater than or equal to 0, and a plurality of input/output (I/O) terminals for inputting and outputting data of the volatile memory cells, and at least one peripheral region that controls a write operation for writing data into the memory regions and a read operation for reading data from the memory regions based on a command and an address input from outside. Thus, a total or entire density of the memory regions corresponds to a non-standard (or ‘interim’) density so that the semiconductor memory device may have an interim density.

Claims

1. A semiconductor memory device comprising:

a plurality of memory regions formed on one chip, each of the memory regions having a plurality of volatile memory cells that are formed as a density of 2̂

K bits, where K is an integer greater than or equal to 0, and a plurality of input/output (I/O) terminals for inputting and outputting data of the volatile memory cells, an entire density of the memory regions corresponding to an interim density; and

at least one peripheral region configured to control a write operation for writing data into the memory regions and a read operation for reading data from the memory regions based on an externally input command and address.

2. The device of claim 1, wherein the memory regions includes:

a first memory region having a plurality of first volatile memory cells that are formed as a density of 2̂

M bits, where M is an integer greater than or equal to 0, and a plurality of first I/O terminals for inputting and outputting data of the first volatile memory cells; and

a second memory region having a plurality of second volatile memory cells that are formed as a density of 2̂

N bits, where N is an integer greater than or equal to 0 and N is different from M, and a plurality of second I/O terminals for inputting and outputting data of the second volatile memory cells.

3. The device of claim 2, wherein a number of the first I/O terminals and/or a number of the second I/O terminals can be expressed as 2̂

L, where L is an integer greater than or equal to 0, respectively.

4. The device of claim 3, wherein the number of the first I/O terminals is the same as the number of the second I/O terminals.

5. The device of claim 3, wherein the number of the first I/O terminals is different from the number of the second I/O terminals.

6. The device of claim 2, wherein the first memory region and the second memory region belong to a same rank of a semiconductor memory module.

7. The device of claim 6, wherein the first I/O terminals and the second I/O terminals simultaneously operate as chip I/O terminals, and wherein a number of the chip I/O terminals corresponds to a sum of the number of the first I/O terminals and the number of the second I/O terminals.

8. The device of claim 2, wherein the first memory region and the second memory region belong to different ranks of a semiconductor memory module.

9. The device of claim 8, wherein the first I/O terminals and the second I/O terminals selectively operate as chip I/O terminals in response to at least one chip selection signal, and wherein a number of the chip I/O terminals corresponds to the number of the first I/O terminals or the number of the second I/O terminals.

10. The device of claim 1, wherein the semiconductor memory device is included in a semiconductor memory package, and wherein the semiconductor memory package is implemented by a monolithic package, a dual-die package, or a through-silicon via dual-die stack package.

11. An integrated circuit memory device, comprising:

a plurality of memory regions on a same memory chip, each of the memory regions having a respective memory capacity defined in units of bits, wherein a sum of the respective memory capacities of the memory regions on the same memory chip cannot be expressed as a power of 2; and

at least one peripheral region configured to control read or write operations for the plurality of memory regions responsive to address and command signals received from an external memory controller.

12. The device of claim 11, wherein the plurality of memory regions comprise:

a first memory region comprising a plurality of first memory cells having a first memory capacity of 2^M bits, where M is an integer greater than or equal to zero, and a plurality of first input/output terminals coupled to the memory cells; and

a second memory region comprising a plurality of second memory cells having a second memory capacity of 2^N bits, where N is an integer greater than or equal to zero and N does not equal M, and a plurality of second input/output terminals coupled to the memory cells,

wherein a sum of the first memory capacity and the second memory capacity is not a power of 2.

13. The device of claim 12, further comprising:

an I/O connecting block configured to connect the first and/or second input/output terminals to chip input/output terminals of the same memory chip.

14. The device of claim 13, wherein a quantity of the chip input/output terminals is not a power of 2.

15. The device of claim 13, wherein a quantity of the chip input/output terminals corresponds to a sum of a quantity of the first and second input/output terminals, and wherein the I/O connecting block is configured to simultaneously connect the first and second input/output terminals to the chip input/output terminals.

16. The device of claim 13, wherein a quantity of the chip input/output terminals corresponds to a quantity of the first input/output terminals or a quantity of the second input/output terminals, and wherein the I/O connecting block is configured to selectively connect either the first input/output terminals or the second input/output terminals to the chip input/output terminals responsive to at least one chip select signal.

17. The device of claim 16, wherein the integrated circuit memory device comprises a first memory chip in a multi-chip memory package, and wherein the memory package comprises a monolithic package, a multi-die package, and/or a through-silicon via multi-die stack package.

18. The device of claim 17, wherein the multi-chip memory package further includes a second memory chip having the first memory region and the second memory region, and wherein the I/O connecting block is configured to simultaneously connect the second input/output terminals of the first and second memory chips to the chip input/output terminals responsive to the chip select signal.

19. The device of claim 18, wherein the chip input/output terminals comprise first chip terminals and second chip terminals different from the first chip terminals, and wherein the I/O connecting block is configured to simultaneously connect the second input/output terminals of the first and second memory chips to the first and second chip terminals, respectively, responsive to the chip select signal.

20. An integrated circuit memory device, comprising:

a plurality of memory regions on a same memory chip, the plurality of memory regions comprising a first memory region comprising a plurality of first volatile memory cells having a first memory capacity of 2^M bits, where M is an integer greater than or equal to zero, and a plurality of first input/output terminals coupled to the memory cells, and a second memory region comprising a plurality of second volatile memory cells having a second memory capacity of 2^N bits, where N is an integer greater than or equal to zero and N does not equal M, and a plurality of second input/output terminals coupled to the memory cells, wherein a sum of the first memory capacity and the second memory capacity cannot be expressed as a power of 2;

an I/O connecting block configured to connect the first and/or second input/output terminals to chip input/output terminals of the same memory chip, wherein the I/O connecting block is configured to simultaneously connect the first and second input/output terminals to the chip input/output terminals or is configured to selectively connect either the first input/output terminals or the second input/output terminals to the chip input/output terminals responsive to at least one chip select signal; and

at least one peripheral region configured to control read or write operations for the plurality of memory regions responsive to address and command signals received from an external memory controller.