SELF ALIGNING VIA PATTERNING

• US 20120302057A1
• Filed: 07/26/2012
• Published: 11/29/2012
• Est. Priority Date: 05/27/2011
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Arnold, John Christopher, Burns, Sean D., Kanakasabapathy, Sivananda K., Yin, Yunpeng
• Granted Patent: US 8,518,824 B2
• Time in Patent Office: Days
• US Class Current: 438/637
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/0338 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76811 involving multiple stacked pre-patterned masks
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665

Abstract

A method for patterning self-aligned vias in a dielectric. The method includes forming a first trench partially through a hard mask, where the trench corresponds to a desired wiring path in the dielectric. The trench should be formed on a sub-lithographic scale. Then, form a second trench, also of a sub-lithographic scale, that intersects the first trench. The intersection forms a pattern extending through the depth of the hard mask, and corresponds to a via hole in the dielectric. The via hole is etched into the dielectric through the hard mask. Then the first trench is extended through the hard mask and the exposed area is etched to form the wiring path, which intersects the via hole. Conductive material is deposited to form a sub-lithographic via and wiring. This method may be used to form multiple vias of sub-lithographic proportions and with a sub-lithographic pitch.

Claims

1. A method for patterning a self-aligned via in a dielectric, the method comprising the steps of:

forming a hard mask on top of a dielectric;

forming a first trench within the hard mask, wherein the first trench extends partially through a depth of the hard mask;

forming a second trench within the hard mask, wherein the second trench intersects at least a portion of the first trench, and wherein the intersection of the first and second trench creates a hole pattern extending through the depth of the hard mask to expose a first area of the dielectric;

etching the exposed first area of the dielectric to create a via hole extending into the dielectric;

exposing a second area of the dielectric by re-etching the first trench to extend through the depth of the hard mask, wherein the exposed second area of the dielectric includes the via hole;

etching the exposed area of the dielectric corresponding to the first trench to create a wiring path in the dielectric, wherein the wiring path extends partially through a depth of the dielectric and wherein the wiring path intersects the via hole; and

depositing a conductive material into the via hole and wiring path of the dielectric to form a metal layer.

2. The method of claim 1, wherein the first trench is formed using one of:

sidewall image transfer and pitch splitting.

3. The method of claim 1, wherein the second trench is formed using one of:

sidewall image transfer and pitch splitting.

4. The method of claim 1, wherein the hard mask is a metal hard mask.

5. The method of claim 4, wherein the metal hard mask comprises a metal containing layer between a first and second oxide layer.

6. The method of claim 5, wherein the step of forming the first trench within the hard mask, wherein the first trench extends partially through a depth of the hard mask, comprises etching the first trench through the first oxide layer and the metal containing layer, but not through the second oxide layer;

and

wherein the step of forming the second trench within the hard mask, wherein the second trench intersects at least a portion of the first trench, and wherein the intersection of the first and second trench creates a hole pattern extending through the depth of the hard mask to expose a first area of the dielectric, comprises, etching the second trench, intersecting the first trench, selective to the metal containing layer such that the second trench stops at the metal containing layer except where the metal containing layer has been removed for forming the first trench thereby extending the second trench to the dielectric at the intersection of the first and second trench.

7. The method of claim 6, wherein the step of etching the first trench through the first oxide layer and the metal containing layer, but not the through the second oxide layer, comprises:

etching the first oxide layer selective to the metal containing layer; and

etching the metal containing layer selective to the second oxide layer.

8. The method of claim 5, wherein the metal containing layer comprises Titanium Nitride.

9. The method of claim 1, wherein dimensions of the via hole are defined by widths of the intersecting first and second trench.

10. A method for patterning self-aligned vias in a dielectric, the method comprising the steps of:

forming a hard mask on top of a dielectric;

forming a first set of trenches within the hard mask, wherein the first set of trenches extends partially through a depth of the hard mask;

forming a second set of trenches within the hard mask, wherein a plurality of the second set of trenches intersects a plurality of the first set of trenches, and wherein the intersection of the plurality of the first set and the plurality of the second set creates a plurality of hole patterns extending through the depth of the hard mask to expose a first area of the dielectric;

etching the exposed first area of the dielectric to create a plurality of via holes extending into the dielectric;

exposing a second area of the dielectric by re-etching the first set of trenches to extend through the depth of the hard mask, wherein the exposed second area of the dielectric includes the plurality of via holes;

etching the exposed area of the dielectric corresponding to the first set of trenches to create wiring paths in the dielectric, wherein the wiring paths extend partially through a depth of the dielectric and wherein the wiring paths intersect the plurality of via holes; and

depositing a conductive material into the plurality of via holes and wiring paths of the dielectric to form a metal layer.

11. The method of claim 10, wherein the first set of trenches are created using a patterning technique such that spacing between a plurality of the first set of trenches is on a sub-lithographic scale.

12. The method of claim 11, wherein the plurality of via holes are etched with a sub-lithographic pitch.

13. The method of claim 11, wherein the patterning technique is selected from the group consisting of sidewall image transfer and pitch splitting.

14. The method of claim 10, wherein the step of forming the first set of trenches within the hard mask comprises etching the first set of trenches through the first oxide layer and the metal containing layer, but not through the second oxide layer;

and

wherein the step of forming the second set of trenches within the hard mask comprises etching the second set of trenches, each intersecting one or more trenches from the first set of trenches, selective to the metal containing layer such that the second set of trenches stops at the metal containing layer except where the metal containing layer has been removed for forming the first set of trenches thereby extending each trench from the second set trenches to the dielectric where each respective trench from the second set of trenches intersects one or more trenches from the first set of trenches.