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SELF ALIGNING VIA PATTERNING

  • US 20120302057A1
  • Filed: 07/26/2012
  • Published: 11/29/2012
  • Est. Priority Date: 05/27/2011
  • Status: Active Grant
First Claim
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1. A method for patterning a self-aligned via in a dielectric, the method comprising the steps of:

  • forming a hard mask on top of a dielectric;

    forming a first trench within the hard mask, wherein the first trench extends partially through a depth of the hard mask;

    forming a second trench within the hard mask, wherein the second trench intersects at least a portion of the first trench, and wherein the intersection of the first and second trench creates a hole pattern extending through the depth of the hard mask to expose a first area of the dielectric;

    etching the exposed first area of the dielectric to create a via hole extending into the dielectric;

    exposing a second area of the dielectric by re-etching the first trench to extend through the depth of the hard mask, wherein the exposed second area of the dielectric includes the via hole;

    etching the exposed area of the dielectric corresponding to the first trench to create a wiring path in the dielectric, wherein the wiring path extends partially through a depth of the dielectric and wherein the wiring path intersects the via hole; and

    depositing a conductive material into the via hole and wiring path of the dielectric to form a metal layer.

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