RUNTIME RECONFIGURABLE DATAFLOW PROCESSOR

• US 20120303932A1
• Filed: 05/24/2012
• Published: 11/29/2012
• Est. Priority Date: 05/27/2011
• Status: Active Grant

• Current Assignee: New York University
• Original Assignee: New York University
• Inventors: LeCun, Yann, Farabet, Clément
• Granted Patent: US 10,078,620 B2
• Time in Patent Office: Days
• US Class Current: 712/30
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06N 3/045 Combinations of networks
• CPC Class Codes: G06N 3/10 Interfaces, programming languages or software development kits, e.g. for simulating neural networks
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A processor includes a plurality of processing tiles, wherein each tile is configured at runtime to perform a configurable operation. A first subset of tiles are configured to perform in a pipeline a first plurality of configurable operations in parallel. A second subset of tiles are configured to perform a second plurality of configurable operations in parallel with the first plurality of configurable operations. The process also includes a multi-port memory access module operably connected to the plurality of tiles via a data bus configured to control access to a memory and to provide data to two or more processing tiles simultaneously. The processor also includes a controller operably connected to the plurality of tiles and the multi-port memory access module via a runtime bus. The processor configures the tiles and the multi-port memory access module to execute a computation.

Claims

1. A processor comprising:

a plurality of processing tiles, wherein each processing tile is configured at runtime to perform a configurable operation, wherein a first subset of processing tiles are configured to perform in a pipeline a first plurality of configurable operations in parallel, and wherein a second subset of processing tiles are configured to perform a second plurality of configurable operations in parallel with the first plurality of configurable operations;

a multi-port memory access module operably connected to the plurality of processing tiles via data lines, wherein the multi-port memory access module is configured to;

control access to a memory; and

provide data to two or more processing tiles simultaneously; and

at least one controller operably connected to the plurality of processing tiles and the multi-port memory access module via a runtime bus, wherein the at least one controller is adapted to configure the plurality of processing tiles and the multi-port memory access module to execute a computation.

2. The processor of claim 1, wherein each of the plurality of processing tiles comprise:

a multiplexer configured to;

receive input data from the multi-port memory access module or from another processing tile;

send output data to the multi-port memory access module or to another processing tile; and

a plurality of operators each operably connected to the multiplexer, wherein each operator is configured to;

receive the input data from the multiplexer;

perform an operation on the input data to generate the output data; and

send the output data to the multiplexer.

3. The processor of claim 2, wherein only a single operator of the plurality of operators is active.

4. The processor of claim 2, wherein the controller is configured to activate one of the plurality of operators for one or more of the plurality of processing tiles.

5. The processor of claim 1, wherein the controller is configured to send a configuration packet to one or more of the plurality of processing tiles, wherein the one or more of the plurality of the processing tiles are configured to activate an operator based upon the configuration packet.

6. The processor of claim 1, wherein the controller is configured to send a configuration packet to the multi-port memory access module, and wherein the multi-port memory access module is configured to connect one or more ports to one or more of the plurality of the processing tiles.

7. The processor of claim 1, wherein one or more of the plurality of the processing tiles are configured to connect to another configuration tile.

8. The processor of claim 7, wherein the controller is configured to reconfigure the connections between the one or more of the plurality of the processing tiles.

9. The processor of claim 1, wherein one or more of the plurality of the processing tiles are configured to connect to the multi-port memory access module.

10. The processor of claim 9, wherein the controller is configured to reconfigure the connections between the one or more of the plurality of the processing tiles and the multi-port memory access module.

11. The processor of claim 1, wherein the controller is configured to configure the plurality of processing tiles and the multi-port memory access module to perform a two or more convolutions.

12. The processor of claim 11, wherein the controller is configured to configure the plurality of processing tiles and the multi-port memory access module to perform the two or more convolutions in parallel with one another.

13. The processor of claim 11, wherein the controller is further configured to configure the plurality of processing tiles and the multi-port memory access module to sum the two or more convolutions.

14. The processor of claim 13, wherein the controller is further configured to configure the plurality of processing tiles and the multi-port memory access module to perform an operation on the sum of the two or more convolutions.

15. The processor of claim 1, wherein the controller is configured to configure a subset of the plurality of processing tiles.

16. The processor of claim 1, wherein each of the plurality of processing tiles is uniquely addressable.

17. A method comprising:

sending, from a controller, a first configuration packet to one or more processing tiles;

receiving, at the one or more processing tiles, the first configuration packet;

selecting, at the one or more processing tiles, an operation to execute based upon the received first configuration packet;

sending, from the controller, a second configuration packet to a multi-port memory access module; and

connecting a subset of the one or more processing tiles to the multi-port memory access module based upon the second configuration packet.

18. The method of claim 17, further comprising connecting a subset of the one or more processing tiles to another configuration tile based upon the first configuration packet.

19. The method of claim 17, further comprising:

receiving data at one or more of the one or more processing tiles from the multi-port memory access module; and

executing the operation on the received data to generate output data.

20. The method of claim 19, further comprising:

sending the output data to a corresponding processing tile; and

executing the operation on the received output data to generate second output data.

21. The method of claim 20, further comprising sending the second output data to the multi-port memory access module.

22. The method of claim 20, further comprising sending the second output data to another processing tile.

23. The method of claim 17, wherein each of the one or more of processing tiles is uniquely addressable.

24. The method of claim 17, further comprising:

sending, from the controller, a third configuration packet to the one or more processing tiles;

receiving, at the one or more processing tiles, the third configuration packet;

selecting, at the one or more processing tiles, another operation to execute based upon the received third configuration packet;

sending, from the controller, a fourth configuration packet to the multi-port memory access module; and

connecting a second subset of the one or more processing tiles to the multi-port memory access module based upon the fourth configuration packet.

25. A processor comprising:

a plurality of processing tiles, wherein each processing tile is configured to perform an operation;

a multi-port memory access module operably connected to the plurality of processing tiles via data lines, wherein the multi-port memory access module is configured to control access to a memory;

at least one controller operably connected to the plurality of processing tiles and the multi-port memory access module via a runtime bus, wherein the at least one controller is adapted to configure the plurality of processing tiles and the multi-port memory access module to execute a computation.