TILE-BASED PROCESSOR ARCHITECTURE MODEL FOR HIGH-EFFICIENCY EMBEDDED HOMOGENEOUS MULTICORE PLATFORMS

• US 20120303933A1
• Filed: 01/31/2011
• Published: 11/29/2012
• Est. Priority Date: 02/01/2010
• Status: Active Grant

• Current Assignee: Bertrand Rousseau, Philippe Manet
• Original Assignee: Bertrand Rousseau, Philippe Manet
• Inventors: Manet, Philippe, Rousseau, Bertrand
• Granted Patent: US 9,275,002 B2
• Time in Patent Office: Days
• US Class Current: 712/30
• CPC Class Codes: G06F 15/17337 Direct connection machines, e.g. completely connected computers, point to point communication networks coupling between buses G06F13/4004
• CPC Class Codes: G06F 15/17343 wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture reconfigurable processors arrays G06F15/7867
• CPC Class Codes: G06F 15/7842 on one IC chip (single chip microcontrollers)
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3888 controlled by a single instruction for multiple threads [SIMT] in parallel
• CPC Class Codes: G06F 9/3891 organised in groups of units sharing resources, e.g. clusters
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present invention relates to a processor which comprises processing elements that execute instructions in parallel and are connected together with point-to-point communication links called data communication links (DCL). The instructions use DCLs to communicate data between them. In order to realize those communications, they specify the DCLs from which they take their operands, and the DCLs to which they write their results. The DCLs allow the instructions to synchronize their executions and to explicitly manage the data they manipulate. Communications are explicit and are used to realize the storage of temporary variables, which is decoupled from the storage of long-living variables.

Claims

1. A processor allowing to execute threads of instructions in parallel comprising

one or more instruction memories comprising a plurality of instruction bundles comprising one or more instructions,

a plurality of point-to-point communication means, hereafter called data communication links, wherein data can be stored, comprising

a write port wherein data can be written by performing a write operation and wherein information about write operation availability can be obtained,

a read port wherein data can be read following a predefined order in relation to the sequence of write operations previously performed on said write port by performing a read operation and wherein information about read operation availability can be obtained,

a plurality of processing means, hereafter called processing elements

wherein said instructions are executed by processing input data obtained from one or more said data communication link read ports and by writing the data produced by the execution to one or more said data communication write ports,

wherein data stored in the data communication links can be explicitly managed by performing said read and write operations provided by said data communication links based on instruction data,

wherein data communications between instructions executed on said processing elements are only performed using said data communication means,

wherein said instruction executions on said processing elements are synchronized based on read and write operation information availability provided by said data communication links,

wherein for each instruction memory there is one of said processing elements that is a branch unit providing an address of a next said instruction bundle to execute.

2. The processor of claim 1,

wherein said processing elements are further grouped in tiles,

wherein a set of said data communication link read ports are connected to said tile inputs and are shared between said tile processing elements and

wherein a set of said communication link write ports are connected to said tile outputs and are shared between said tile processing elements and

wherein one or more of said communication links have their write port connected to one tile output, and their read port connected to a different tile input.

wherein said instructions executed in a same said tile follows a predefined order based on priority specified in said executed instruction data,

3. The processor of claim 2,

wherein said tiles are further grouped in clusters comprising each

a single instruction memory,

a single branch unit processing element,

wherein said cluster instruction memory provides an instruction bundle to each said cluster tiles based on said address provided by said cluster branch unit,

4. The processor of claim 3 wherein some processing elements are storage means allowing to store program long-living variables

5. The processor of claim 4, wherein data communication links can perform additional operations comprising

a data read operation that does not consume data stored in said communication link,

a data write operation that forces a write operation in said data communication link even when write operation is not available,

a flush operation that erase all data stored in said data communication links.

6. The processor of claim 5,

wherein each processing element further comprises one control mean providing control signals based on

instruction data, processing element input data communication link availability information, and

processing element output data communication link availability information,

wherein each tile further comprises one control mean providing control signals to handle instruction

execution coordination in the processing element and providing a control signal notifying the last

execution cycle for the instruction executed in the processing element,

wherein each cluster further comprises a control mean providing a control signal notifying that the cluster is allowed to execute the next instruction, based on control signals provided by said tile control means.

7. The processor of claim 6,

wherein all control means are centralized in a single control mean.

8. The processor of claim 6, wherein each tile further comprises

one selection mean

comprising one or several input ports connected to said data communication link read ports,

comprising one or several output ports connected to processing element inputs,

wherein information is provided to each said processing element control mean about one or more said

data communication link read port read operation availabilities, based on control signals from said

processing mean control mean,

wherein data from one or more said data communication link read port is provided to each said

processing element input based on control signals from said processing element control mean,

wherein operations are performed on said data communication link read ports based on control signals

from said processing element control mean, and

one distribution mean

comprising one or several input ports connected to processing element outputs and said processing mean control means,

comprising one or several output ports connected to said data communication link write ports,

wherein information is provided to each said processing mean control mean about said data

communication link write port write operation availabilities,

wherein data is provided to one or several said data communication link write ports from said

processing element outputs based on control signals from said processing element control means,

wherein operations are performed on said data communication link write ports based on control signals

from said processing element control mean.

9. The processor of claim 8,

wherein each tile further comprises a plurality of selection means and wherein each tile processing element inputs are partitioned in one or several groups, and a separate said selection mean is attributed to each group and only a subset of all tile data communication link read ports is connected to said selection mean inputs.

wherein each tile further comprises a plurality of distribution means wherein data communication link write ports are partitioned in several groups, and one separate said distribution mean is attributed to each group, and where only a subset of processing element outputs are connected to said distribution mean inputs.

10. The processor of claim 6, wherein said instruction memories provide signals to the cluster control means notifying the availability of the fetched instruction bundle.

11. A method allowing to execute a program on the processor of claim 3, the method comprising

a) reading an instruction bundle from each cluster instruction memory;

b) executing the instructions in processing elements when the data communication links specified by the instructions providing data to said processing elements are all available for read operations and data communication links specified by the instructions that receives the data computed by the processing elements are all available for write operations;

c) performing a write operation on the data communication links where data is distributed, as specified by the instructions;

d) performing a read operation on the data communication links from where data is provided to the functional units, as specified by the instructions;

e) computing the address of the next instruction bundle to fetch in the branch unit;

f) requesting a fetch of the next instruction bundle when all instructions from the current bundle are executed.

12. The method of claim 11, the instruction execution step further restricting instruction execution inside each tile with the verification that instructions executed in said tile can be executed only if all other instructions with a higher priority in said tile have been executed first.