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TILE-BASED PROCESSOR ARCHITECTURE MODEL FOR HIGH-EFFICIENCY EMBEDDED HOMOGENEOUS MULTICORE PLATFORMS

  • US 20120303933A1
  • Filed: 01/31/2011
  • Published: 11/29/2012
  • Est. Priority Date: 02/01/2010
  • Status: Active Grant
First Claim
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1. A processor allowing to execute threads of instructions in parallel comprisingone or more instruction memories comprising a plurality of instruction bundles comprising one or more instructions,a plurality of point-to-point communication means, hereafter called data communication links, wherein data can be stored, comprisinga write port wherein data can be written by performing a write operation and wherein information about write operation availability can be obtained,a read port wherein data can be read following a predefined order in relation to the sequence of write operations previously performed on said write port by performing a read operation and wherein information about read operation availability can be obtained,a plurality of processing means, hereafter called processing elementswherein said instructions are executed by processing input data obtained from one or more said data communication link read ports and by writing the data produced by the execution to one or more said data communication write ports,wherein data stored in the data communication links can be explicitly managed by performing said read and write operations provided by said data communication links based on instruction data,wherein data communications between instructions executed on said processing elements are only performed using said data communication means,wherein said instruction executions on said processing elements are synchronized based on read and write operation information availability provided by said data communication links,wherein for each instruction memory there is one of said processing elements that is a branch unit providing an address of a next said instruction bundle to execute.

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