BIT ERROR REDUCTION THROUGH VARIED DATA POSITIONING

• US 20120304039A1
• Filed: 05/29/2012
• Published: 11/29/2012
• Est. Priority Date: 05/27/2011
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Fusion-IO Incorporated (Western Digital Corporation)
• Inventors: Peterson, Jim, Strasser, John, Hyun, Jea
• Granted Patent: US 9,176,810 B2
• Time in Patent Office: Days
• US Class Current: 714/773
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: H03M 13/05 using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits H03M13/2906 takes precedence

Abstract

Devices, apparatuses, systems, and methods are disclosed for bit error reduction through varied data positioning. A write request module is configured to receive data for storage in an array of solid-state storage elements. The solid-state storage elements are accessible in parallel. A write module is configured to store the data in parallel to the array of solid-state storage elements with varied data positions for the data relative to different solid-state storage elements of the array. A read module is configured to read the data in parallel from the array of solid-state storage elements.

Claims

1. A method for varied data positioning, the method comprising:

receiving data for storage in an array of solid-state storage elements, the solid-state storage elements accessible in parallel;

storing the data to the array of solid-state storage elements in parallel, the data stored in a plurality of different data positions relative to solid-state storage elements of the array; and

reading the data in parallel from the different data positions relative to solid-state storage elements of the array.

2. The method of claim 1, further comprising determining a different address for each of the different data positions according to a deterministic pattern.

3. The method of claim 2, further comprising sending the different addresses in parallel to the solid-state storage elements of the array to store the data and to read the data.

4. The method of claim 2, wherein the deterministic pattern comprises adding a predetermined offset to addresses to define each of the different data positions according to an order of the solid-state storage elements of the array to determine the different addresses.

5. The method of claim 1, wherein the data is stored as a logical page spanning logical erase blocks of the array of solid-state storage elements such that a physical page of a physical erase block of the logical erase blocks is not unused.

6. The method of claim 1, wherein the different data positions comprise one or more of solid-state storage dies having different relative positions within the solid-state storage elements of the array, physical pages disposed in different positions relative to the solid-state storage elements of the array, one or more upper pages and one or more lower pages of the solid-state storage elements of the array, physical erase blocks disposed in different physical positions relative to the solid-state storage elements of the array, and one or more odd physical pages and one or more even physical pages of the array of solid-state storage elements.

7. The method of claim 1, wherein the data comprises a logical page of data and the different data positions comprise physical pages disposed in different positions relative to the solid-state storage elements of the array.

8. The method of claim 7, further comprising inverting an address bit for solid-state storage elements of the array to alternate the different data positions between the one or more upper pages and the one or more lower pages of the multi-level memory cells.

9. The method of claim 7, further comprising restructuring logical pages of the array of solid-state storage elements from physical pages disposed in similar positions relative to the solid-state storage elements of the array to the physical pages disposed in different positions in response to a number of program/erase cycles satisfying a threshold.

10. The method of claim 7, further comprising buffering the data with other data such that the data and the other data is stored to the physical pages in an order that satisfies a write order for the solid-state storage elements of the array.

11. An apparatus for varied data positioning, the apparatus comprising:

a write request module configured to receive data for storage in an array of solid-state storage elements, the solid-state storage elements accessible in parallel;

a write module configured to store the data in parallel to the array of solid-state storage elements with varied data positions for the data relative to different solid-state storage elements of the array; and

a read module configured to read the data in parallel from the different solid-state storage elements of the array.

12. The apparatus of claim 11, further comprising an address module configured to determine a different address for each of the varied data positions according to a deterministic pattern and to send the different addresses in parallel to the solid-state storage elements of the array.

13. The apparatus of claim 11, wherein enable lines are electrically coupled to the different solid-state storage elements of the array in different relative locations of the different solid-state storage elements such that the array of solid-state storage elements is configured to receive the data in parallel at the varied data positions.

14. The apparatus of claim 11, wherein the varied data positions comprise solid-state storage dies having different relative positions within the different solid-state storage elements of the array.

15. The apparatus of claim 11, wherein the data comprises a logical page of data and the varied data positions comprise physical pages disposed in different positions relative to the different solid-state storage elements of the array.

16. The apparatus of claim 15, wherein the array of solid-state storage elements comprises multi-level memory cells and the physical pages disposed in different positions comprise one or more upper pages and one or more lower pages of the multi-level memory cells.

17. The apparatus of claim 15, wherein the logical page spans more than one logical erase block of the array of solid-state storage elements.

18. The apparatus of claim 11, wherein the varied data positions comprise physical erase blocks disposed in different physical positions relative to the different solid-state storage elements of the array.

19. The apparatus of claim 11, wherein the varied data positions comprise one or more odd physical pages and one or more even physical pages of the array of solid-state storage elements.

20. The apparatus of claim 11, wherein the varied data positions comprise a combination of two or more of solid-state storage dies having different relative positions within the different solid-state storage elements of the array, one or more upper pages and one or more lower pages of the array of solid-state storage elements, and physical pages disposed in different positions relative to the different solid-state storage elements of the array.

21. The apparatus of claim 11, wherein the varied data positions are selected to average an error rate across the array of solid-state storage elements.

22. A system for varied data positioning, the system comprising:

a solid-state storage device comprising an array of solid-state storage elements, the solid-state storage elements accessible in parallel; and

a storage controller for the solid-state storage device, the storage controller comprising,

a write module configured to store an error correcting code chunk in parallel across the array of solid-state storage elements, portions of the error correcting code chunk stored in a plurality of different locations relative to different solid-state storage elements of the array, the different locations comprising different error rates; and

a read module configured to read the portions of the error correcting code chunk in parallel from the array of solid-state storage elements.

23. The system of claim 22, further comprising a host computing system in communication with the solid-state storage device over one or more communications buses.

24. A computer program product comprising a computer readable storage medium storing computer usable program code executable to perform operations for varied data positioning, the operations of the computer program product comprising:

determining a plurality of different addresses for each of a plurality of different data positions relative to different solid-state storage elements of an array of solid-state storage elements accessible in parallel;

sending the plurality of different addresses in parallel to the solid-state storage elements of the array; and

storing data in parallel to the array of solid-state storage elements at the plurality of different data positions of the plurality of different addresses.

25. An apparatus for varied data positioning, the apparatus comprising:

means for receiving data for storage in an array of solid-state storage elements, the solid-state storage elements accessible in parallel;

means for storing the data to the array of solid-state storage elements in parallel, the data stored in different data positions relative to different solid-state storage elements of the array, the different data positions selected to average an error rate across the array; and

means for reading the data in parallel from the array of solid-state storage elements.