TRANSISTOR DEVICE

• US 20120305893A1
• Filed: 02/21/2011
• Published: 12/06/2012
• Est. Priority Date: 02/19/2010
• Status: Abandoned Application

• Current Assignee: University College Cork (Higher Education Authority)
• Original Assignee: University College Dublin
• Inventors: Colinge, Jean-Pierre
• Application Number:
  US13/579,825
• Publication Number:
  US 20120305893A1
• Time in Patent Office: Days
• US Class Current: 257/29
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 2029/7857 of the accumulation type
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

The invention provides transistor device comprising a source, a drain and a connecting channel, the channel is a nano-structure device adapted to allow current flow between the source and drain. The channel comprises an ultra-high doping concentration and is of the same polarity as in the source and/or drain. Essentially the transistor device of the present invention acts as a junctionless, highly-doped gated resistor. In the context of optimal performance of the transistor high doping means equal to or exceeds 1×10¹⁹ atom/cm³ results in that the device can operate as a junctionless transistor device.

Claims

1. A transistor device comprising a source, a drain and a connecting channel,

the channel is a nano-structure device adapted to allow current flow between the source and drain;

the channel comprises an ultra-high doping concentration and is of the same polarity as in the source and/or drain.

2. The device as claimed in claim 1 wherein the ultra-high doping concentration is equal to or exceeds 1×

1019 atom/cm3.

3. The device as claimed in claim 1 wherein the channel is degenerately doped.

4. The device as claimed in claim 1 wherein the ultra-high doping concentration channel is adapted to act like a quasi metallic channel.

5. The device as claimed in claim 1 wherein the nano-structure device is a nano-wire.

6. The device as claimed in claim 1 wherein the device is positioned on a bulk silicon substrate.

7. The device as claimed in claim 1 wherein the device is positioned on a bulk silicon substrate and the device is electrically isolated from the bulk silicon substrate.

8. The device as claimed in claim 7 comprising an insulator layer positioned below the interface between the channel and silicon substrate.

9. The device as claimed in claim 1 wherein the source, the drain and connecting channel comprises a N ^-N -N device to provide a junction-less device.

10. The device as claimed in claim 1 wherein the source, the drain and connecting channel comprises a P -P -P device to provide a junction-less device.

11. The device as claimed in claim 1 wherein the doping concentration of a selected value can be used in the channel region and the source and drain extension regions.

12. The device as claimed in claim 11 comprising spacer technology adapted to be used to locally increase the outer source and drain regions to a concentration above the selected value.

13. The device as claimed in claim 1 wherein the nano-structure device comprises a planar device.

14. A channel device for use in a transistor to connect a source region and drain region, said channel comprising an ultra-high doping concentration.

15. A multi-gate structure on a bulk silicon substrate comprising a transistor device as claimed in claim 1.

16. A process for making a transistor device comprising the steps of:

arranging one or more nano-device on a substrate, for example a silicon substrate;

implanting ultra high doping concentration in said nano-wire to define a channel region; and

depositing a gate material to cooperate with said one or more nano-wires, said gate material is adapted to control current flow through said channel region by applying a charge to the gate material.

17. The process of claim 16 wherein the ultra-high doping concentration is equal to or exceeds 1×

10¹⁹ atom/cm³.

18. A memory device comprising a transistor device, said transistor device comprising a source, a drain and a connecting channel,

the channel is a nano-structure device adapted to allow current flow between the source and drain;

the channel comprises an ultra-high doping concentration and is of the same polarity as in the source and/or drain.