TRANSISTOR DEVICE
First Claim
1. A transistor device comprising a source, a drain and a connecting channel,the channel is a nano-structure device adapted to allow current flow between the source and drain;
- the channel comprises an ultra-high doping concentration and is of the same polarity as in the source and/or drain.
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Accused Products
Abstract
The invention provides transistor device comprising a source, a drain and a connecting channel, the channel is a nano-structure device adapted to allow current flow between the source and drain. The channel comprises an ultra-high doping concentration and is of the same polarity as in the source and/or drain. Essentially the transistor device of the present invention acts as a junctionless, highly-doped gated resistor. In the context of optimal performance of the transistor high doping means equal to or exceeds 1×1019 atom/cm3 results in that the device can operate as a junctionless transistor device.
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Citations
18 Claims
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1. A transistor device comprising a source, a drain and a connecting channel,
the channel is a nano-structure device adapted to allow current flow between the source and drain; the channel comprises an ultra-high doping concentration and is of the same polarity as in the source and/or drain.
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2. The device as claimed in claim 1 wherein the ultra-high doping concentration is equal to or exceeds 1×
- 1019 atom/cm3.
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3. The device as claimed in claim 1 wherein the channel is degenerately doped.
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4. The device as claimed in claim 1 wherein the ultra-high doping concentration channel is adapted to act like a quasi metallic channel.
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5. The device as claimed in claim 1 wherein the nano-structure device is a nano-wire.
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6. The device as claimed in claim 1 wherein the device is positioned on a bulk silicon substrate.
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7. The device as claimed in claim 1 wherein the device is positioned on a bulk silicon substrate and the device is electrically isolated from the bulk silicon substrate.
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8. The device as claimed in claim 7 comprising an insulator layer positioned below the interface between the channel and silicon substrate.
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9. The device as claimed in claim 1 wherein the source, the drain and connecting channel comprises a N -N -N device to provide a junction-less device.
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10. The device as claimed in claim 1 wherein the source, the drain and connecting channel comprises a P -P -P device to provide a junction-less device.
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11. The device as claimed in claim 1 wherein the doping concentration of a selected value can be used in the channel region and the source and drain extension regions.
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12. The device as claimed in claim 11 comprising spacer technology adapted to be used to locally increase the outer source and drain regions to a concentration above the selected value.
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13. The device as claimed in claim 1 wherein the nano-structure device comprises a planar device.
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14. A channel device for use in a transistor to connect a source region and drain region, said channel comprising an ultra-high doping concentration.
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15. A multi-gate structure on a bulk silicon substrate comprising a transistor device as claimed in claim 1.
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16. A process for making a transistor device comprising the steps of:
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arranging one or more nano-device on a substrate, for example a silicon substrate; implanting ultra high doping concentration in said nano-wire to define a channel region; and depositing a gate material to cooperate with said one or more nano-wires, said gate material is adapted to control current flow through said channel region by applying a charge to the gate material.
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17. The process of claim 16 wherein the ultra-high doping concentration is equal to or exceeds 1×
- 1019 atom/cm3.
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18. A memory device comprising a transistor device, said transistor device comprising a source, a drain and a connecting channel,
the channel is a nano-structure device adapted to allow current flow between the source and drain; the channel comprises an ultra-high doping concentration and is of the same polarity as in the source and/or drain.
Specification