HIGH DENSITY MEMORY CELLS USING LATERAL EPITAXY

• US 20120305998A1
• Filed: 05/31/2011
• Published: 12/06/2012
• Est. Priority Date: 05/31/2011
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Booth, Roger A. Jr., Cheng, Kangguo, Ervin, Joseph, Fried, David M., Kim, Byeong, Pei, Chengwen, Todi, Ravi M., Wang, Geng
• Granted Patent: US 8,829,585 B2
• Time in Patent Office: Days
• US Class Current: 257/304
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/92 Capacitors having potential barriers
• CPC Class Codes: H10B 12/038 the capacitor being in a trench in the substrate
• CPC Class Codes: H10B 12/37 the capacitor being at least partially in a trench in the substrate

Abstract

In a vertical dynamic memory cell, monocrystalline semiconductor material of improved quality is provided for the channel of an access transistor by lateral epitaxial growth over an insulator material (which complements the capacitor dielectric in completely surrounding the storage node except at a contact connection structure, preferably of metal, from the access transistor to the storage node electrode) and etching away a region of the lateral epitaxial growth including a location where crystal lattice dislocations are most likely to occur; both of which features serve to reduce or avoid leakage of charge from the storage node. An isolation structure can be provided in the etched region such that space is provided for connections to various portions of a memory cell array.

Claims

1. A memory cell including

a storage node surrounded by dielectric except at a contact thereto, and

an access transistor having a channel formed of monocrystalline semiconductor material devoid of crystal lattice dislocations above a portion of said storage node, wherein a portion of said dielectric prevents lattice defects from propagating to said semiconductor material from a material forming said storage node.

2. A memory cell as recited in claim 1, wherein said storage node comprises a deep trench capacitor.

3. A memory cell as recited in claim 1, wherein said memory cell is formed in and on a semiconductor-on-insulator (SOI) structure wherein a portion of said dielectric is substantially coplanar with an insulator layer of said SOI structure and said monocrystalline semiconductor material is substantially coplanar with an active semiconductor layer of said SOI structure.

4. A memory cell as recited in claim 3, wherein said SOI structure has an active semiconductor layer having a thickness of 10 nm or less.

5. A memory cell as recited in claim 1, further including shallow trench isolation adjacent said access transistor.

6. A memory cell as recited in claim 5, further including conductors formed on said shallow trench isolation.

7. A memory cell as recited in claim 1, further including a metal connection between said access transistor and said storage node.

8. A semiconductor device including a memory cell comprising

a storage node surrounded by dielectric except at a contact thereto, and

an access transistor having a channel formed of monocrystalline semiconductor material devoid of crystal lattice dislocations above a portion of said storage node, wherein a portion of said dielectric prevents lattice defects from propagating to said semiconductor material from a material forming said storage node.

9. A semiconductor device as recited in claim 8, wherein said storage node comprises a deep trench capacitor.

10. A semiconductor device as recited in claim 8, wherein said memory cell is formed in and on a semiconductor-on-insulator (SOI) structure wherein a portion of said dielectric is substantially coplanar with an insulator layer of said SOI structure and said monocrystalline semiconductor material is substantially coplanar with an active semiconductor layer of said SOI structure.

11. A semiconductor device as recited in claim 10, wherein said SOI structure has an active semiconductor layer having a thickness of 10 nm or less.

12. A semiconductor device as recited in claim 8, further including shallow trench isolation adjacent said access transistor.

13. A semiconductor device as recited in claim 12, further including conductors formed on said shallow trench isolation.

14. A semiconductor device as recited in claim 8, further including a metal connection between said access transistor and said storage node.

15. A method of manufacture of a semiconductor device including a memory cell, said method including steps of

forming an opening in a semiconductor layer formed on an insulator,

forming a storage node through said opening,

depositing an insulator layer over said storage node,

forming a monocrystalline semiconductor layer by lateral epitaxial growth from said semiconductor layer over said insulator layer,

etching a portion of said monocrystalline semiconductor layer to remove any crystal lattice dislocation resulting from said lateral epitaxial growth,

forming an isolation structure in a volume created by said etching step, and

forming a transistor in a remaining portion of said monocrystalline semiconductor layer.

16. A method as recited in claim 15, including a further step of

forming conductors on said isolation structure.

17. A method as recited in claim 15, including a further step of

forming a metal connection between said transistor and said storage node.

18. A method as recited in claim 17, including a further step of

forming a further metal connection to said transistor.

19. A method as recited in claim 15, wherein said insulator is formed substantially coplanar with said insulator.

20. The method as recited in claim 15, wherein said monocrystalline semiconductor material has a thickness of 10 nm or less.