BEOL STRUCTURES INCORPORATING ACTIVE DEVICES AND MECHANICAL STRENGTH

• US 20120306018A1
• Filed: 05/31/2011
• Published: 12/06/2012
• Est. Priority Date: 05/31/2011
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Gates, Stephen M., Edelstein, Daniel C., Nitta, Satyanarayana V.
• Granted Patent: US 8,624,323 B2
• Time in Patent Office: Days
• US Class Current: 257/368
• CPC Class Codes: H01L 21/02667 Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5228 Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 24/80 Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/016 Thin-film circuits
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/66984 Devices using spin polarized carriers
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/12032 Schottky diode
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/1306 Field-effect transistor [FET]

Abstract

A monolithic integrated circuit and method includes a substrate, a plurality of semiconductor device layers monolithically integrated on the substrate, and a metal wiring layer with vias interconnecting the plurality of semiconductor device layers. The semiconductor device layers are devoid of bonding or joining interface with the substrate. A method of fabricating a monolithic integrated circuit using a single substrate, includes fabricating semiconductor devices on a substrate, fabricating at least one metal wiring layer on the semiconductor devices, forming at least one dielectric layer in integral contact with the at least one metal wiring layer, forming contact openings through the at least one dielectric layer to expose regions of the at least one metal wiring layer, integrally forming, from the substrate, a second semiconductor layer on the dielectric layer, and in contact with the at least one metal wiring layer through the contact openings, and forming a plurality of non-linear semiconductor devices in said second semiconductor layer.

Claims

1. A monolithic integrated circuit, comprising:

a substrate;

a plurality of semiconductor device layers monolithically integrated on the substrate; and

a metal wiring layer with vias interconnecting the plurality of semiconductor device layers.

2. The monolithic integrated circuit according to claim 1, wherein the plurality of semiconductor device layers are devoid of bonding or joining interfaces to the substrate.

3. The monolithic integrated circuit according to claim 1, further comprising a first dielectric layer deposited on the metal wiring layer,

wherein the plurality of semiconductor device layers are interconnected by the metal wiring layer constructed within the first dielectric layer.

4. The monolithic integrated circuit according to claim 3, wherein a second dielectric layer is deposited on one of the plurality of semiconductor device layers.

5. The monolithic integrated circuit according to claim 3, wherein the first dielectric layer comprises a SiN layer or a SiCN layer located atop the metal wiring layer, and

wherein at least one underlying damascene Cu wiring level is formed on a semiconductor device layer of the plurality of semiconductor device layers, the semiconductor device layer being integrally formed from the substrate.

6. The monolithic integrated circuit according to claim 1, further comprising a plurality of nonlinear devices fabricated in the plurality of semiconductor device layers.

7. The monolithic integrated circuit according to claim 1, wherein nonlinear devices are formed within a semiconductor device layer of the plurality of semiconductor device layers, the nonlinear devices being selected from at least one of varactors, field effect transistors, bipolar transistors, spin-enhanced field effect transistors, tunneling transistors, ferroelectric gate field effect transistors, tunnel diodes, junction diodes, photoemitters, lasers, photodetectors, waveguides, and photonic modulators.

8. The monolithic integrated circuit according to claim 1, wherein linear devices are formed within a semiconductor device layer of the plurality of semiconductor device layers, the linear devices being selected from at least one of interconnects, metal thin film resistors, inductors, metal-insulator-metal (MIM) capacitors.

9. The monolithic integrated circuit according to claim 1, further comprising a nonlinear device formed on at least one of the plurality of semiconductor device layers, the nonlinear device including a first conductor contacting a principal electrically conducting channel, a second conductor contacting the principal electrically conducting channel, and a control electrode, the control electrode regulating a current flow between the first conductor and the second conductor of the principal electrically conducting channel,

wherein the nonlinear device includes the first conductor, the second conductor and control electrode connected to at least one metal wiring level from a plurality of the metal wiring layers.

10. The monolithic integrated circuit according to claim 1, wherein at least one of the plurality of semiconductor device layers includes a plurality of transistors, and

wherein gate, source, and drain contacts of the transistors are connected to a metal wiring level from the metal wiring layer comprising an overlying damascene Cu wiring level located above the transistors.

11. The monolithic integrated circuit according to claim 10, wherein the gate, source, and drain contacts of the transistors are fabricated through a second dielectric layer deposited as an encapsulation layer surrounding the semiconductor device.

12. The monolithic integrated circuit according to claim 11, wherein a silicon oxide layer is located at least on an upper interface or a lower interface between at least one of the semiconductor device layers and one of the first or second dielectric layers.

13. The monolithic integrated circuit according to claim 1, further comprising a nonlinear device formed on at least one of the plurality of semiconductor device layers, the nonlinear device including a first conductor contacting a first semiconductor region of a first conductivity type and a second conductor contacting a semiconductor region of a second conductivity type, the first and second semiconductor regions providing a junction exhibiting a non-linear voltage-current characteristic for the nonlinear device between the first and second conductors,

wherein the first and second conductors are connected to at least one of a plurality of metal wiring levels in a plurality of the metal wiring layers.

14. The monolithic integrated circuit according to claim 1, wherein at least one of the plurality of semiconductor devices includes a plurality of nonlinear devices including at least first and second conductors,

wherein the at least first and second conductors of the nonlinear devices are connected to a metal wiring level of the metal wiring layer comprising an overlying damascene Cu wiring level located above the nonlinear devices, and

wherein at least the first and second conductors of the nonlinear devices are fabricated through a second dielectric layer deposited as an encapsulation layer surrounding the first and second conductors.

15. The monolithic integrated circuit according to claim 14, wherein an intrinsic stress in the first and second dielectric layers is adjusted to a predetermined amount to minimize a net curvature of the substrate after completion of said second dielectric layer, and

wherein a silicon oxide layer is located at least on an upper interface or a lower interface between at least one of the semiconductor device layers and one of the first or second dielectric layers.

16. A monolithic integrated circuit, comprising:

a substrate comprising a first semiconductor layer;

a first wiring layer formed on the substrate;

a first dielectric layer, including the first wiring layer, formed on the substrate;

a second semiconductor layer comprising an active device formed on the first dielectric layer and monolithically integrated with the substrate;

a second dielectric layer formed on the second semiconductor layer; and

a second wiring layer formed on the second dielectric layer.

17. The monolithic integrated circuit according to claim 16, wherein the second semiconductor layer is located in a BEOL (back-end-of-line) interconnect structure, and

wherein the second semiconductor layer comprises the active device formed on the first dielectric layer devoid of a bonding interface or a joining interface therebetween the second semiconductor layer and the first dielectric layer.

18. The monolithic integrated circuit according to claim 16, wherein the second semiconductor device layer is discontinuous across the substrate, and

wherein the first and second semiconductor device layers are formed on the substrate devoid of bonding or joining interfaces.

19. The monolithic integrated circuit according to claim 16, wherein the active device is selected from at least one of varactors, field effect transistors, bipolar transistors, spin-enhanced field effect transistors, tunneling transistors, ferroelectric gate field effect transistors, tunnel diodes, junction diodes, photoemitters, lasers, photodetectors, waveguides, photonic modulators, interconnects, metal thin film resistors, inductors, and metal-insulator-metal (MIM) capacitors.

20. A method of fabricating a monolithic integrated circuit using a single substrate, the method comprising:

forming a first semiconductor layer from a substrate;

fabricating semiconductor devices on the substrate;

fabricating at least one metal wiring layer on the semiconductor devices;

forming at least one dielectric layer in integral contact with the at least one metal wiring layer;

forming contact openings through the at least one dielectric layer to expose regions of the at least one metal wiring layer;

integrally forming, from the substrate, a second semiconductor layer on the dielectric layer, and in contact with the at least one metal wiring layer through the contact openings; and

forming a plurality of non-linear semiconductor devices in said second semiconductor layer.

21. The method according to claim 20, wherein the forming of a second semiconductor layer includes a low-temperature deposition step and a low thermal budget recrystallization step.

22. The method according to claim 21, wherein the recrystallization step is performed by one of rapid thermal annealing, pulsed continuous-wave laser annealing, nanosecond-pulsed laser annealing, and ultraviolet-light-assisted annealing.

23. The method according to claim 22, further comprising depositing a layer of a passivation dielectric on the second semiconductor layer,

wherein the passivation dielectric has an internal stress greater than 20 GPa.

24. The monolithic integrated circuit according to claim 20, wherein the second semiconductor layer includes a plurality of transistors,

wherein gate, source, and drain contacts of the transistors are connected to a metal wiring level from the at least one metal wiring layer comprising an overlying damascene Cu wiring level located above the transistors,

wherein the gate, source, and drain contacts of the transistors are fabricated through a second dielectric layer deposited as an encapsulation layer surrounding the semiconductor devices,

wherein an intrinsic stress in the first and second dielectric layers is adjusted to minimize a net curvature of the substrate after completion of the second dielectric layer, and

wherein a silicon oxide layer is located at least on an upper interface or a lower interface between at least one of the semiconductor device layers and one of the first or second dielectric layers.

25. The method according to claim 20, further comprising forming at least two types of interconnects including a first metal wiring layer and a second metal wiring layer within the first dielectric layer, the two types of interconnects comprising through-vias that other than which pass through the second semiconductor layer, and shallow vias that make electrical contact to the plurality of non-linear semiconductor devices,

wherein the first dielectric layer or the second dielectric layer is planarized to remove topography, and

wherein the first and second semiconductor layers are devoid of bonding or joining interfaces to the substrate.