Edge termination configurations for high voltage semiconductor power devices

• US 20120306044A1
• Filed: 05/31/2011
• Published: 12/06/2012
• Est. Priority Date: 05/31/2011
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Bobde, Madhur, Lui, Sik K., Bhalla, Anup
• Granted Patent: US 8,643,135 B2
• Time in Patent Office: Days
• US Class Current: 257/488
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

This invention discloses a semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area wherein the edge termination area comprises a wide trench filled with a field-crowding reduction filler and a buried field plate buried under a top surface of the semiconductor substrate and laterally extended over a top portion of the field crowding field to move a peak electric field laterally away from the active cell area. In a specific embodiment, the field-crowding reduction filler comprises a silicon oxide filled in the wide trench.

Claims

1. A semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area wherein:

the edge termination area comprises a wide trench filled with a field-crowding reduction filler adjacent to an cylindrical junction between the active cell area and the edge termination area; and

a buried field plate buried under a top surface of the semiconductor substrate in the edge termination area and laterally extended in the wide trench away from the active cell area to move a peak electric field laterally away from the active cell area.

2. The semiconductor power device of claim 1 wherein:

the field-crowding reduction filler comprises a silicon oxide filled in the wide trench.

3. The semiconductor power device of claim 1 wherein:

the edge termination area has a width ranging from 10 microns to 60 microns and said wide trench has a width ranging from 5 microns to 50 microns.

4. The semiconductor power device of claim 1 wherein:

the buried field plate is buried under the top surface of the semiconductor substrate at a depth ranging from 1.5 microns to 5 microns.

5. The semiconductor power device of claim 1 wherein:

the buried field plate is buried under the top surface of the semiconductor substrate and above a depletion region at a bottom surface of a body region of the cylindrical junction.

6. The semiconductor power device of claim 1 wherein:

the buried field plate is buried under the top surface of the semiconductor substrate and below a depletion region at a bottom surface of a body region of the cylindrical junction.

7. The semiconductor power device of claim 1 wherein:

the field-crowding reduction filler comprises electrical insulating dielectric material filled in the wide trench.

8. The semiconductor power device of claim 1 wherein:

the buried field plate is buried under the top surface of the semiconductor substrate in the edge termination area and laterally extended over the top portion of the wide trench from the cylindrical junction to a lateral distance ranging from 5 microns to 30 microns.

9. The semiconductor power device of claim 1 wherein:

the wide trench in the edge termination area is disposed adjacent to a body region disposed next to an outer edge of the active cell area and the buried field plate further has a top portion covering a part of a top surface of the body region and a vertical portion extends vertically downward along an inner sidewall of the wide trench to connected to the buried field plate buried in the wide trench.

10. The semiconductor power device of claim 9 further comprising:

a thin insulation layer disposed between the body region and the vertical portion of the buried field plate disposed along the inner sidewall of the wide trench.

11. The semiconductor power device of claim 1 further comprising:

a metal oxide semiconductor field effect transistor (MOSFET) device.

12. The semiconductor power device of claim 1 further comprising:

an insulated gate transistor (IGBT) device.

13. A method to manufacture a semiconductor power device in a semiconductor substrate with an active cell area and an edge termination area comprising:

open a wide trench in the edge termination area and filling the wide trench with a field-crowding reduction filler followed by etching the field-crowding reduction filler down to a level below a top surface of said wide trench; and

forming a buried field plate along a sidewall of said wide trench and cover a top surface of said field-crowing reduction filler followed by filling the wide trench with the field-crowding reduction filler thus burying the buried filed plate in the wide trench below the top surface of the trench.

14. The method of claim 13 wherein:

the step of filling the wide trench with the field-crowding reduction filler comprises a step of filling the wide trench with silicon oxide.

15. The method of claim 13 wherein:

the step of opening the wide trench in the edge termination area further comprising a step of opening the wide trench with a width ranging from 5 microns to 50 microns in the edge termination area having a width ranging from 10 microns to 60 microns.

16. The method of claim 13 wherein:

the step of etching the field-crowding reduction filler down to a level below a top surface of said wide trench further comprising a step of etching the field-crowding reduction filler down to a depth ranging from 1.5 microns to 5 microns below the top surface of the wide trench.

17. The method of claim 13 wherein:

the step of opening the wide trench in the edge termination area further comprising a step of opening a plurality of narrow trenches in the edge termination area followed by oxidizing the semiconductor substrate between the narrow trenches to function as the field-crowding reduction filler then filling the narrow trenches by depositing the field-crowding reduction filler.

18. The method of claim 13 wherein:

the buried field plate is buried under the top surface of the semiconductor substrate and above a depletion region at a bottom surface of a P-body region of the cylindrical junction the step of etching the field-crowding reduction filler down to a level below a top surface of said wide trench further comprising a step of etching the field-crowding reduction filler down to a depth above a depletion region at a bottom surface of a body

19. The method of claim 13 wherein:

the buried field plate is buried under the top surface of the semiconductor substrate and above a depletion region at a bottom surface of a P-body region of the cylindrical junction the step of etching the field-crowding reduction filler down to a level below a top surface of said wide trench further comprising a step of etching the field-crowding reduction filler down to a depth below a depletion region at a bottom surface of a body region of a cylindrical junction

20. The method of claim 13 wherein:

the step of opening the wide trench in the edge termination area further comprising a step of opening the wide trench adjacent to a body region disposed next to an outer edge of the active cell area and by forming the buried field plate with a top portion covering a part of a top surface of the body region and a vertical portion extends vertically downward along the sidewall of the wide trench to connected to the buried field plate buried in the wide trench.