APPARATUSES INCLUDING STAIR-STEP STRUCTURES AND METHODS OF FORMING THE SAME

• US 20120306089A1
• Filed: 06/02/2011
• Published: 12/06/2012
• Est. Priority Date: 06/02/2011
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Freeman, Eric H., Smith, Michael A.
• Granted Patent: US 8,530,350 B2
• Time in Patent Office: Days
• US Class Current: 257/773
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/32133 by chemical means only
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/76892 modifying the pattern
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/50 characterised by the boundary region between the core region and the peripheral circuit region
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

Methods for forming semiconductor structures are disclosed, including a method that involves forming sets of conductive material and insulating material, forming a first mask over the sets, forming a first number of contact regions, forming a second mask over a first region of the sets, and removing material from of the sets in a second, exposed region laterally adjacent the first region to form a second number of contact regions. Another method includes forming first and second contact regions on portions of sets of conductive materials and insulating materials, each of the second contact regions more proximal to an underlying substrate than each of the first contact regions. Apparatuses such as memory devices including laterally adjacent first and second regions each including contact regions of a different portion of a plurality of conductive materials and related methods of forming such devices are also disclosed.

Claims

1. A method of forming a semiconductor structure, comprising:

forming a plurality of sets of conductive material and insulating material;

forming a first mask over a topmost set of the plurality of sets;

removing a portion of the first mask to expose a portion of a major surface of the topmost set of the plurality of sets;

removing the exposed portion of the topmost set of the plurality of sets;

removing another portion of the first mask to expose another portion of the major surface of the topmost set, the another portion of the major surface of the topmost set adjacent to the removed portion of the major surface of the topmost set of the plurality of sets;

repeating the removing a portion of the first mask and removing the exposed portion of the topmost set of the plurality of sets until a first number of contact regions are formed, each contact region offset from the other contact regions;

forming a second mask over a first region of the plurality of sets; and

removing material from the plurality of sets in a second, exposed region of the plurality of sets laterally adjacent the first region to form a second number of contact regions.

2. The method of claim 1, wherein removing an exposed portion of the topmost set of the plurality of sets comprises:

anisotropically etching a conductive material of the topmost set; and

anisotropically etching an insulating material of the topmost set.

3. The method of claim 1, wherein forming a plurality of sets of conductive material and insulating material comprises forming each set of the plurality to comprise the insulating material on a side of the conductive material opposite a substrate.

4. The method of claim 1, wherein removing material comprises removing all of the insulating material and conductive material from one-half of the plurality of sets in the second, exposed region.

5. The method of claim 1, wherein removing an exposed portion of the topmost set of the plurality of sets comprises removing an exposed portion of one set of the plurality of sets.

6. The method of claim 1, wherein removing an exposed portion of the topmost set of the plurality of sets comprises anisotropically etching through portions of two sets of the plurality of sets.

7. The method of claim 1, wherein repeating the removing a portion of the first mask and removing the exposed portion of the topmost set of the plurality of sets until a first number of contact regions are formed comprises forming the contact regions on one-half of a total number of sets of the plurality of sets, each contact region comprising a step, each step having an end portion offset from an end portion of an adjacent step.

8. The method of claim 1, wherein repeating the removing a portion of the first mask and removing the exposed portion of the topmost set of the plurality of sets until a first number of contact regions are formed comprises forming the contact regions on one-fourth of a total number of sets of the plurality of sets.

9. The method of claim 1, wherein removing material comprises forming steps in the second, exposed region of the plurality of sets, each step in the first region of the plurality of sets having an end portion offset from an end portion of an adjacent step in the second, exposed region.

10. The method of claim 1, further comprising forming contacts in contact with each of the contact regions.

11. The method of claim 1, wherein forming a second mask over a first region of the plurality of sets and removing material from the plurality of sets in a second, exposed region of the plurality of sets laterally adjacent the first region are performed before forming a first mask over a topmost set of the plurality of sets, removing a portion of the first mask to expose a portion of a major surface of the topmost set of the plurality of sets, and removing the exposed portion of the topmost set of the plurality of sets.

12. The method of claim 1, wherein forming a second mask over a first region of the plurality of sets and removing material from the plurality of sets in a second, exposed region of the plurality of sets laterally adjacent the first region are performed after forming a first mask over a topmost set of the plurality of sets, removing a portion of the first mask to expose a portion of a major surface of the topmost set of the plurality of sets, and removing the exposed portion of the topmost set of the plurality of sets.

15. The method of claim 12, further comprising removing a portion of the sets of conductive materials and insulating materials not covered by the another mask to form third contact regions and fourth contact regions, wherein each of the third and fourth contact regions is more proximal to a underlying substrate than each of the first and second contact regions.

13. A method of forming a semiconductor structure, comprising:

forming first contact regions on portions of sets of conductive materials and insulating materials, each first contact region offset from the other first contact regions;

forming a mask over a region of the sets of conductive materials and insulating materials; and

removing a portion of the sets of conductive materials and insulating materials not covered by the mask to form second contact regions, wherein each of the second contact regions is more proximal to an underlying substrate than each of the first contact regions.

14. The method of claim 13, further comprising forming another mask over a portion of the first contact regions and a portion of the second contact regions.

16. A method of forming a vertical memory device, comprising:

forming a plurality of alternating word line connections and insulating materials;

forming contact regions on portions of the word line connections, each contact region offset from the other contact regions;

forming a mask over a region of the plurality of alternating word line connections and insulating materials;

removing a portion of the word line connections and insulating materials not covered by the mask to form additional contact regions on other portions of the word line connections of the plurality; and

forming contacts in connection with each contact region and each additional contact region.

17. An apparatus, comprising:

a plurality of sets of conductive material and insulative material, the plurality of sets comprising;

a first region of the plurality of sets comprising contact regions of a first portion of the plurality of sets; and

a second region of the plurality of sets laterally adjacent the first region comprising contact regions of a second portion of the plurality of sets, wherein the contact regions of the first region are offset from the contact regions of the second region.

18. The apparatus of claim 17, wherein:

the contact regions of the first region comprise contact regions of first alternating sets of the plurality of sets; and

the contact regions of the second region comprise second alternating sets of the plurality of sets.

19. The apparatus of claim 17, wherein the plurality of sets is formed over a substrate and wherein the contact regions of the first region are more proximate to the substrate than the contact regions of the second region.

20. The apparatus of claim 17, further comprising:

a third region of the plurality of sets laterally adjacent the second region comprising contact regions of a third portion of the plurality of sets; and

a fourth region of the plurality of sets laterally adjacent the third region comprising contact regions of a fourth portion of the plurality of sets, wherein the contact regions of the second region are offset from the contact regions of the third region and the contact regions of the third region are offset form the contact regions of the fourth region.

21. The apparatus of claim 20, wherein the contact regions of the first region are offset from the contact regions of the third region and the contact regions of the second region are offset from the contact regions of the fourth region.

22. An apparatus, comprising:

a vertical memory array region comprising a plurality of conductive materials; and

a stair-step region comprising the plurality of conductive materials and including a first region and a second region laterally adjacent the first region, the first region including contact regions of a first portion of the plurality of conductive materials and the second region including contact regions of a second portion of the plurality of conductive materials different than the first portion, wherein each contact region of the first region is offset from each contact region of the second region.

23. The apparatus of claim 22, wherein the stair-step region further comprises:

a third region laterally adjacent the first region comprising contact regions of a third portion of the plurality of conductive materials different than both the first and second portions; and

a fourth region laterally adjacent the second region comprising contact regions of a fourth portion of the plurality of conductive materials different than the first, second, and third portions.

24. The apparatus of claim 22, further comprising a plurality of contacts, each contact of the plurality of contacts electrically connected to a respective one of the contact regions.

25. The apparatus of claim 22, wherein the vertical memory array and stair-step regions are formed over a substrate, and each contact region of the second region is closer to the substrate than a respective adjacent one of the contact regions of the first region.

26. A method of forming a semiconductor structure, the method comprising:

forming a plurality of sets of conductive material and insulating material;

removing a first portion of a topmost set of the plurality of sets;

forming a mask over a first region of a second portion of the topmost set, wherein a second region of the second portion of the topmost set is exposed; and

removing the second portion of the topmost set in the second region, wherein the second portion of the topmost set in the first region comprises a first contact region and a portion of a set underlying the second portion of the topmost set in the second region comprises a second contact region.

27. The method of claim 26, wherein forming a mask over a first region of a second portion of the topmost set comprises forming a stair-step mask over the first region of the second portion of the topmost set.

28. The method of claim 26, wherein forming a mask over a first region of a second portion of the topmost set comprises forming a chop mask over the first region of the second portion of the topmost set.