METHOD AND MODEL OF CARBON NANOTUBE BASED THROUGH SILICON VIAS (TSV) FOR RF APPLICATIONS

• US 20120306096A1
• Filed: 05/30/2012
• Published: 12/06/2012
• Est. Priority Date: 05/30/2011
• Status: Abandoned Application

• Current Assignee: Board of Trustees of The University of Alabama (University of Alabama System)
• Original Assignee: Board of Trustees of The University of Alabama (University of Alabama System)
• Inventors: Kim, Bruce, Kannan, Sukeshwar, Gupta, Anurag, Mohammed, Falah, Ahn, Byoungchul
• Application Number:
  US13/483,270
• Publication Number:
  US 20120306096A1
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 30/00 Nanotechnology for materials or surface science, e.g. nanocomposites
• CPC Class Codes: H01L 2221/1094 Conducting structures comprising nanotubes or nanowires
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/53276 containing carbon, e.g. fullerenes superconducting fullerenes H10N60/853
• CPC Class Codes: H01L 29/413 Nanosized electrodes, e.g. nanowire electrodes comprising one or a plurality of nanowires nanosized carbon materials, e.g. carbon nanotubes, per se C01B32/15; transparent electrodes comprising carbon nano-tubes H10K30/821, nanotechnology per se B82B
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A carbon nanotube (CNT) through silicon via (TSV) for three-dimensional (3D) substrate interconnects is described. TSV technologies provide for high performance and high density 3D packages. The CNT-based TSVs provide for integration of analog, RF and mixed-signal integrated circuits. CNT-based TSV provides superior electrical characteristics as compared to conventional TVs filled with conductive metals.

Claims

1. A semiconductor chip comprising:

a semiconductor chip body formed from silicon;

a carbon nanotube through silicon via that passes through the semiconductor chip body and contacts a metal layer at at least one end; and

an insulating layer that surrounds the carbon nanotube through silicon via.

2. The semiconductor chip as recited in claim 1, wherein the insulating layer is formed from silicon dioxide.

3. The semiconductor chip as recited in claim 1, wherein the carbon nanotube through silicon via is formed as carbon nanotube bundles.

4. The semiconductor chip as recited in claim 3, wherein a height of the carbon nanotube through silicon via is approximately 90 μ

m.

5. The semiconductor chip as recited in claim 3, wherein a diameter of the carbon nanotube through silicon via is approximately 75 μ

m.

6. The semiconductor chip as recited in claim 3, a diameter of each carbon nanotube is approximately 1 nm.

7. The semiconductor chip as recited in claim 3, wherein the carbon nanotube through silicon via is formed from approximately 18761 bundles.

8. The semiconductor chip as recited in claim 1, wherein the insulating layer has a thickness of approximately 0.1 μ

m.

9. The semiconductor chip as recited in claim 1, wherein the semiconductor chip is provided as part of a three-dimensional large-scale integration package.

10. The semiconductor chip as recited in claim 9, wherein the carbon nanotube through silicon via is used as an interconnect within the three-dimensional large-scale integration package.

11. The semiconductor chip as recited in claim 10, wherein the three-dimensional large-scale integration package is provided within a RF application having a frequency of between 20 GHz and 80 GHz.

12. An integrated circuit (IC) through-silicon via (TSV) structure comprising:

a plurality of carbon nanotube bundles disposed within an integrated circuit package;

and an insulating layer that surrounds the plurality carbon nanotube bundles.

13. The IC as recited in claim 12, wherein a height of the carbon nanotube bundles is approximately 90 μ

m.

14. The IC as recited in claim 12, wherein a diameter of the TSV is approximately 75 μ

m.

15. The IC as recited in claim 12, a diameter of each carbon nanotube within the plurality of carbon nanotube bundles is approximately 1 nm.

16. The IC as recited in claim 12, wherein a number of carbon nanotube bundles is approximately 18761.

17. The IC as recited in claim 12, wherein the insulating layer has a thickness of approximately 0.1 μ

m.

18. A integrated circuit package system comprising:

an integrated circuit die having carbon nanotube through silicon vias each surrounded by an insulating layer, the carbon nanotube through silicon vias each contacting a metallic pad at each of an upper and lower surface of the integrated circuit,

wherein the integrated circuit die is adapted to be assembled into three-dimensional package using the carbon nanotube through silicon vias as interconnects.

19. The system as recited in claim 18, wherein the metallic pad is made from copper.

20. The system as recited in claim 18, wherein the carbon nanotube through silicon vias are provided as carbon nanotube bundles, and wherein each carbon nanotube has a diameter of approximately 1 nm.