Control of Digital Voltage and Frequency Scaling Operating Points

• US 20120306558A1
• Filed: 05/31/2011
• Published: 12/06/2012
• Est. Priority Date: 05/31/2011
• Status: Active Grant

• Current Assignee: Telefonaktiebolaget LM Ericsson
• Original Assignee: Ericsson Modems Sa (Telefonaktiebolaget LM Ericsson)
• Inventors: Bauer, Harald, Singvall, Jakob
• Granted Patent: US 8,799,698 B2
• Time in Patent Office: Days
• US Class Current: 327/298
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: H03K 3/02 Generators characterised by the type of circuit or by the means used for producing pulses H03K3/64 - H03K3/84 take precedence
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A clock signal for electronic circuitry is generated by generating, based on which one of a plurality of application use cases is presently active, a first signal that indicates a first selected one of a plurality of clock signal operating points. Based on the electronic circuitry'"'"'s present speed requirement, a second signal is generated that indicates a second selected one of the clock signal operating points. For any given one of the application use cases, the speed requirement need not remain constant for the duration of the application use case. Based on whichever one of the first and second signals is associated with a higher clock frequency operating point, a third signal is generated that indicates which clock signal operating point (and possibly what voltage level) should be active. The third signal controls generation of a clock (and possibly also voltage level).

Claims

1. A method of generating a clock signal to be supplied to electronic circuitry, the method comprising:

generating, based on which one of a plurality of application use cases capable of being carried out by the electronic circuitry is presently active, a first signal that indicates a first selected one of a plurality of clock signal operating points;

generating, based on a present speed requirement of the electronic circuitry, a second signal that indicates a second selected one of the plurality of clock signal operating points;

generating, based on the first and second signals, a third signal that indicates which of the plurality of clock signal operating points should be active, wherein the clock signal operating point indicated by the third signal is whichever one of the clock signal operating points indicated by the first and second signals is associated with a higher clock signal frequency; and

using the third signal to control generation of a clock signal having the operating point indicated by the third signal,

wherein for any given one of the application use cases, the present speed requirement need not remain constant for the duration of the given one of the application use cases.

2. The method of claim 1, wherein:

the first signal further indicates a first selected one of a plurality of supply voltage levels;

the second signal further indicates a second selected one of the plurality of supply voltage levels;

the third signal further indicates which of the plurality of supply voltage levels should be active; and

the method comprises using the third signal to control generation of a supply voltage level having the supply voltage level indicated by the third signal.

3. The method of claim 1, wherein:

the first signal further indicates a first selected one of a plurality of supply voltage levels;

the second signal further indicates a second selected one of the plurality of supply voltage levels; and

the method comprises;

generating, based on the first and second signals, a fourth signal that indicates which of the plurality of supply voltage levels should be active, wherein the supply voltage level indicated by the fourth signal is the most power consuming one of the supply voltage level indicated by the first signal and the supply voltage level indicated by the second signal; and

using the fourth signal to control generation of a supply voltage level having the supply voltage level indicated by the fourth signal.

4. The method of claim 1, wherein:

the first signal has two states;

the second signal has two states; and

generating the third signal that indicates which of the plurality of clock signal operating points should be active comprises performing a logical OR between the first signal and the second signal.

5. The method of claim 1, wherein:

the first signal has more than two states; and

the second signal has more than two states.

6. The method of claim 1, wherein:

generating the first signal comprises using a programmed processor to select one of the plurality of clock signal operating points based on which of the plurality of application use cases is presently active; and

generating the second signal comprises using a hardwired component to generate the second signal based on the present speed requirement of the electronic circuitry.

7. The method of claim 6, wherein the hardwired component is a timing generator.

8. The method of claim 1, wherein:

the electronic circuitry is configured to perform functions in a mobile communication equipment; and

the present speed requirement of the electronic circuitry is a function of a timing characteristic of a signal received by the mobile communication equipment.

9. The method of claim 1, further comprising:

using the third signal to control generation of one or more other clock signals, each having the clock signal operating point indicated by the third signal, wherein for any given one of the plurality of clock signal operating points, the clock signal and the one or more other clock signals operate at different frequencies relative to one another.

10. The method of claim 1, further comprising:

using the third signal to control generation of one or more other supply voltage levels, wherein for any given one of the plurality of supply voltage levels, the generated supply voltage level and the generated one or more other supply voltage levels are different from one another.

11. The method of claim 1, wherein the second signal changes states while the first signal remains constant during the given one of the application use cases, whereby an average clock frequency during the given one of the application use cases is not equal to any one of a plurality of clock frequencies that respectively correspond to the clock signal operating points.

12. The method of claim 1, comprising:

inhibiting generation of the second signal based on the present speed requirement of the electronic circuitry, and instead generating the second signal as a pulse width modulated signal having a duty cycle that is based on the presently active application use case.

13. The method of claim 12, comprising:

causing the first signal to remain in a deasserted state for the duration of the presently active application use case.

14. An apparatus for generating a clock signal to be supplied to electronic circuitry, the apparatus comprising:

circuitry configured to generate, based on which one of a plurality of application use cases capable of being carried out by the electronic circuitry is presently active, a first signal that indicates a first selected one of a plurality of clock signal operating points;

circuitry configured to generate, based on a present speed requirement of the electronic circuitry, a second signal that indicates a second selected one of the plurality of clock signal operating points;

circuitry configured to generate, based on the first and second signals, a third signal that indicates which of the plurality of clock signal operating points should be active, wherein the clock signal operating point indicated by the third signal is whichever one of the clock signal operating points indicated by the first and second signals is associated with a higher clock signal frequency; and

circuitry configured to use the third signal to control generation of a clock signal having the operating point indicated by the third signal,

wherein for any given one of the application use cases, the present speed requirement need not remain constant for the duration of the given one of the application use cases.

15. The apparatus of claim 14, wherein:

the first signal further indicates a first selected one of a plurality of supply voltage levels;

the second signal further indicates a second selected one of the plurality of supply voltage levels;

the third signal further indicates which of the plurality of supply voltage levels should be active; and

the apparatus comprises circuitry configured to use the third signal to control generation of a supply voltage level having the supply voltage level indicated by the third signal.

16. The apparatus of claim 14, wherein:

the first signal further indicates a first selected one of a plurality of supply voltage levels;

the second signal further indicates a second selected one of the plurality of supply voltage levels; and

the apparatus comprises;

circuitry configured to generate, based on the first and second signals, a fourth signal that indicates which of the plurality of supply voltage levels should be active, wherein the supply voltage level indicated by the fourth signal is the most power consuming one of the supply voltage level indicated by the first signal and the supply voltage level indicated by the second signal; and

circuitry configured to use the fourth signal to control generation of a supply voltage level having the supply voltage level indicated by the fourth signal.

17. The apparatus of claim 14, wherein:

the first signal has two states;

the second signal has two states; and

the circuitry configured to generate the third signal that indicates which of the plurality of clock signal operating points should be active comprises circuitry configured to perform a logical OR between the first signal and the second signal.

18. The apparatus of claim 14, wherein:

the first signal has more than two states; and

the second signal has more than two states.

19. The apparatus of claim 14, wherein:

the circuitry configured to generate the first signal comprises a programmed processor configured to select one of the plurality of clock signal operating points based on which of the plurality of application use cases is presently active; and

the circuitry configured to generate the second signal comprises a hardwired component configured to generate the second signal based on the present speed requirement of the electronic circuitry.

20. The apparatus of claim 19, wherein the hardwired component is a timing generator.

21. The apparatus of claim 14, wherein:

the electronic circuitry is configured to perform functions in a mobile communication equipment; and

the present speed requirement of the electronic circuitry is a function of a timing characteristic of a signal received by the mobile communication equipment.

22. The apparatus of claim 14, further comprising:

circuitry configured to use the third signal to control generation of one or more other clock signals, each having the clock signal operating point indicated by the third signal, wherein for any given one of the plurality of clock signal operating points, the clock signal and the one or more other clock signals operate at different frequencies relative to one another.

23. The apparatus of claim 14, further comprising:

circuitry configured to use the third signal to control generation of one or more other supply voltage levels, wherein for any given one of the plurality of supply voltage levels, the generated supply voltage level and the generated one or more other supply voltage levels are different from one another.

24. The apparatus of claim 14, wherein the circuitry configured to generate the second signal is configured to respond to changes in the present speed requirement that take place during the given one of the application use cases by changing the state of the second signal while the first signal remains constant during the given one of the application use cases, whereby an average clock frequency during the given one of the application use cases is not equal to any one of a plurality of clock frequencies that respectively correspond to the clock signal operating points.

25. The method of claim 14, comprising:

inhibiting generation of the second signal based on the present speed requirement of the electronic circuitry, and instead generating the second signal as a pulse width modulated signal having a duty cycle that is based on the presently active application use case.

26. The method of claim 25, comprising:

causing the first signal to remain in a deasserted state for the duration of the presently active application use case.