MULTILAYER CERAMIC CAPACITOR

• US 20120307418A1
• Filed: 05/23/2012
• Published: 12/06/2012
• Est. Priority Date: 05/31/2011
• Status: Active Grant

• Current Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: KIM, Sang Huk, PARK, Jae Sung, CHOI, Sung Hyuk, SONG, Seon Ki, CHANG, Han Nah
• Granted Patent: US 8,559,160 B2
• Time in Patent Office: Days
• US Class Current: 361/321.2
• CPC Class Codes: H01G 4/01 Form of self-supporting electrodes
• CPC Class Codes: H01G 4/012 Form of non-self-supporting electrodes
• CPC Class Codes: H01G 4/12 Ceramic dielectrics H01G4/085 takes precedence
• CPC Class Codes: H01G 4/30 Stacked capacitors H01G4/33 takes precedence

Abstract

There is provided a multilayer ceramic capacitor. The capacitor includes: a multilayer body having a dielectric layer; and first and second internal electrodes disposed in the multilayer body, the dielectric layer being disposed between the first and second internal electrodes, wherein, in a cross-section taken in a width-thickness direction of the multilayer body, an offset portion is defined as a portion where adjacent first and second internal electrodes do not overlap with each other, and a ratio (t1/td) of a width t1 of the offset portion to a thickness td of the dielectric layer is 1 to 10.

Claims

1. A multilayer ceramic capacitor, comprising:

a multilayer body having a dielectric layer; and

first and second internal electrodes disposed in the multilayer body, the dielectric layer being disposed between the first and second internal electrode;

wherein, in a cross-section taken in a width-thickness direction of the multilayer body, the first and second internal electrodes are offset in a width direction, and an offset portion is defined as a portion where adjacent first and second internal electrodes do not overlap with each other, and

wherein a ratio (t1/td) of a width t1 of the offset portion to a thickness td of the dielectric layer is 1 to 10.

2. The multilayer ceramic capacitor of claim 1, wherein the width t1 is defined as a minimum width of the offset portion, and the thickness td of the dielectric layer is defined as an average thickness of the dielectric layers.

3. The multilayer ceramic capacitor of claim 1, wherein the thickness td of the dielectric layer is 0.65 μ

m or less.

4. The multilayer ceramic capacitor of claim 1, wherein the second internal electrode is alternately offset to the right and left, in the width direction with respect to the first internal electrode.

5. The multilayer ceramic capacitor of claim 1, wherein the width t1 ranges from 0.8 μ

m to 5.8 μ

m.

6. The multilayer ceramic capacitor of claim 1, wherein the multilayer ceramic capacitor has a length and width of 0.6±

0.09 mm and 0.3±

0.09 mm, respectively.

7. The multilayer ceramic capacitor of claim 6, wherein 200 or more dielectric layers are laminated.

8. A multilayer ceramic capacitor, comprising:

a multilayer body having first and second sides;

first and second internal electrodes provided in the multilayer body, and having ends exposed to the first and second sides, respectively; and

a dielectric layer disposed between the first and second internal electrodes and having a thickness td of 0.65 μ

m or less,

wherein, in a width-thickness cross-section of the multilayer body, a ratio (t1/td) of a minimum width t1 of an offset portion to the thickness td of the dielectric layer ranges from 1 to 10,

wherein the offset portion is defined as a portion where adjacent first and second internal electrodes do not overlap to be offset from each other.

9. The multilayer ceramic capacitor of claim 8, wherein the thickness td of the dielectric layer is a distance between the first and second internal electrodes disposed to be adjacent.

10. The capacitor of claim 8, wherein the second internal electrode is alternately offset to the right and left, in the width direction with respect to the first internal electrode.

11. The capacitor of claim 8, wherein the minimum width t1 ranges from 0.8 μ

m to 5.8 μ

m.

12. The multilayer ceramic capacitor of claim 8, wherein the multilayer ceramic capacitor has a length and width of 0.6±

0.09 mm and 0.3±

0.09 mm, respectively.

13. The multilayer ceramic capacitor of claim 12, wherein 200 or more dielectric layers are laminated

14. A multilayer ceramic capacitor, comprising:

a multilayer body having first and second sides;

first and second internal electrodes provided in the multilayer body, and having ends exposed to the first and second sides, respectively,

wherein, in a cross-section of the multilayer body, substantially perpendicular to a first direction thereof, a ratio (t1/td) of a width t1 of an offset portion where the first and second internal electrodes disposed to be adjacently offset from each other in a second direction substantially perpendicular to the first direction, to a distance td between the first and second internal electrodes disposed to be adjacent ranges from 1 to 10.

15. The capacitor of claim 14, wherein the distance td between the first and second internal electrodes disposed to be adjacent is 0.65 μ

m or less.

16. The capacitor of claim 14, wherein the second internal electrode is alternately offset to the right and left, in the width direction with respect to the first internal electrode.

17. The capacitor of claim 14, wherein the width t1 of the offset portion ranges from 0.8 μ

m to 5.8 μ

m.

18. The multilayer ceramic capacitor of claim 14, wherein the width t1 is defined as a minimum width of the offset portion.

19. The multilayer ceramic capacitor of claim 14, wherein the multilayer ceramic capacitor has a length and width of 0.6±

0.09 mm and 0.3±

0.09 mm, respectively.

20. The multilayer ceramic capacitor of claim 19, wherein 200 or more dielectric layers are laminated.