Interleaved Bit Line Architecture for 2T2C Ferroelectric Memories

• US 20120307545A1
• Filed: 06/01/2011
• Published: 12/06/2012
• Est. Priority Date: 06/01/2011
• Status: Abandoned Application

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: McAdams, Hugh P., Summerfelt, Scott R., Ndai, Patrick M.
• Application Number:
  US13/150,885
• Publication Number:
  US 20120307545A1
• Time in Patent Office: Days
• US Class Current: 365/145
• CPC Class Codes: G11C 11/221 using ferroelectric capacitors

Abstract

A ferroelectric memory with interleaved pairs of ferroelectric memory cells of the two-transistor, two-capacitor (2T2C) type. Each memory cell in a given pair is constructed as first and second portions, each portion including a transistor and a ferroelectric capacitor. Within each pair, a first portion of a second memory cell is physically located between the first and second portions of the first memory cell. As a result, complementary bit lines for adjacent columns are interleaved with one another. Each sense amplifier is associated with a multiplexer, so that the adjacent columns of the interleaved memory cells are supported by a single sense amplifier. Noise coupling among the bit lines is reduced, and the sense amplifiers can be placed along one side of the array, reducing the number of dummy cells required to eliminate edge cell effects.

Claims

1. A ferroelectric memory array comprised of two-transistor, two-capacitor ferroelectric memory cells arranged in rows and columns, and arranged as a plurality of pairs of adjacent memory cells, each pair of memory cells comprising:

a first memory cell associated with a first column, comprising;

first and second ferroelectric capacitors, each having a first plate coupled to a plate line, and having a second plate;

a first access transistor having a conduction path connected between the second plate of the first ferroelectric capacitor and a first bit line of the first column, the first access transistor connected to a word line; and

a second access transistor having a conduction path connected between the second plate of the first ferroelectric capacitor and a second bit line of the first column, the first access transistor connected to a word line; and

a second memory cell associated with a second column, comprising;

first and second ferroelectric capacitors, each having a first plate coupled to a plate line, and having a second plate;

a first access transistor having a conduction path connected between the second plate of the first ferroelectric capacitor and a first bit line of the second column, the first access transistor connected to a word line; and

a second access transistor having a conduction path connected between the second plate of the first ferroelectric capacitor and a second bit line of the second column, the first access transistor connected to a word line;

wherein the first and second bit lines of the first and second columns are parallel to one another;

wherein the first ferroelectric capacitor and the first access transistor of the second memory cell is disposed between the first and second ferroelectric capacitors of the first memory cell, so that the first bit line of the second column is disposed between the first and second bit lines of the first column;

and wherein the second ferroelectric capacitor and the second access transistor of the first memory cell is disposed between the first and second ferroelectric capacitors of the second memory cell, so that the second bit line of the first column is disposed between the first and second bit lines of the second column.

2. The memory array of claim 1, further comprising:

a plurality of sense amplifiers, each associated with a pair of columns of memory cells; and

a plurality of multiplexers, each associated with one of the sense amplifiers, each multiplexer having inputs receiving the first and second bit lines from each of its associated pair of columns, having outputs coupled to complementary inputs of its associated sense amplifier, and having select inputs receiving control signals corresponding to a column address;

wherein each multiplexer is controlled, responsive to its select inputs, to selectively couple the first and second bit lines from one of its associated pair of columns, or the first and second bit lines from the other of its associated pair of columns, to the complementary inputs of its associated sense amplifier.

3. The memory array of claim 2, wherein each of the plurality of sense amplifiers is coupled to a local input/output line extending across the array in a direction parallel with the bit lines of each column;

and wherein, within each pair of memory cells, a local input/output line is disposed between one of the bit lines for the first column and one of the bit lines for the second column.

4. The memory array of claim 2, wherein each of the plurality of sense amplifiers is coupled to a complementary pair of local input/output lines extending across the array in a direction parallel with the bit lines of each column;

and wherein, within each pair of memory cells, a first one of a pair of local input/output lines is disposed between the first bit line for the first column and one of the bit lines for the second column, and a second one of the pair of local input/output lines is disposed between the first bit line for the second column and one of the bit lines for the first column.

5. The memory array of claim 1, wherein the gates of the first and second transistor for the first memory cell of each pair are connected to a word line for a first row;

and wherein the gates of the first and second transistor for the second memory cell of each pair are connected to a word line for a second row adjacent to the first row.

6. An array of ferroelectric memory cells at a surface of a semiconductor body, the memory cells arranged in rows and columns within a first memory array block, each memory cell including two portions, each portion including a transistor and a ferroelectric capacitor, the memory cells arranged in interleaved pairs, each interleaved pair of memory cells comprising:

first and second active regions for first and second portions, respectively, of a first memory cell;

first and second active regions for first and second portions, respectively, of a second memory cell, the first portion of the second memory cell disposed at the surface between the first and second portions of the first memory cell of the pair;

a first polysilicon element disposed over the first and second active regions of the first and second portions of the first memory cell, the first polysilicon element defining source/drain regions in each of the first and second active regions on either side thereof;

a second polysilicon element disposed over the first and second active regions of the first and second portions of the second memory cell, the second polysilicon element defining source/drain regions in each of the first and second active regions on either side thereof;

a first ferroelectric capacitor in connection with, and overlying at least a portion of, one of the source/drain regions of the first active region of the first memory cell;

a second ferroelectric capacitor in connection with, and overlying at least a portion of, one of the source/drain regions of the second active region of the first memory cell;

a third ferroelectric capacitor in connection with, and overlying at least a portion of, one of the source/drain regions of the first active region of the second memory cell, the third ferroelectric capacitor disposed between the first and second ferroelectric capacitors;

a fourth ferroelectric capacitor in connection with, and overlying at least a portion of, one of the source/drain regions of the first active region of the second memory cell, so that the second ferroelectric capacitor is disposed between the third and fourth ferroelectric capacitors;

first true and complementary bit lines formed in metal conductors and parallel with one another, each in connection with and overlying at least a portion of the first and second active regions, respectively, of the first memory cell; and

second true and complementary bit lines formed in metal conductors and parallel with one another and with the first true and complementary bit lines, each of the second true and complementary bit lines in connection with and overlying at least a portion of the first and second active regions, respectively, of the second memory cell, the second true bit line disposed between the first true and complementary bit lines, and the first complementary bit line disposed between the second true and complementary bit lines.

7. The memory array of claim 6, further comprising:

a first bank of sense amplifiers associated with the first memory array block, each sense amplifier in the first bank of sense amplifiers associated with first true and complementary bit lines for a first column of memory cells, and with second true and complementary bit lines for a second column of memory cells, the first and second column of memory cells adjacent to one another and associated with first and second memory cells in a corresponding column of interleaved pairs of memory cells.

8. The memory array of claim 7, wherein the first bank of sense amplifiers is disposed on a single side of the first memory array block.

9. The memory array of claim 8, further comprising a second memory array block of memory cells arranged in rows and columns;

each memory cell including two portions, each portion including a transistor and a ferroelectric capacitor, the memory cells arranged in interleaved pairs, each interleaved pair of memory cells comprising;

first and second active regions for first and second portions, respectively, of a first memory cell;

first and second active regions for first and second portions, respectively, of a second memory cell, the first portion of the second memory cell disposed at the surface between the first and second portions of the first memory cell of the pair;

a first polysilicon element disposed over the first and second active regions of the first and second portions of the first memory cell, the first polysilicon element defining source/drain regions in each of the first and second active regions on either side thereof;

a second polysilicon element disposed over the first and second active regions of the first and second portions of the second memory cell, the second polysilicon element defining source/drain regions in each of the first and second active regions on either side thereof;

a first ferroelectric capacitor in connection with, and overlying at least a portion of, one of the source/drain regions of the first active region of the first memory cell;

a second ferroelectric capacitor in connection with, and overlying at least a portion of, one of the source/drain regions of the second active region of the first memory cell;

a third ferroelectric capacitor in connection with, and overlying at least a portion of, one of the source/drain regions of the first active region of the second memory cell, the third ferroelectric capacitor disposed between the first and second ferroelectric capacitors;

a fourth ferroelectric capacitor in connection with, and overlying at least a portion of, one of the source/drain regions of the first active region of the second memory cell, so that the second ferroelectric capacitor is disposed between the third and fourth ferroelectric capacitors;

first true and complementary bit lines formed in metal conductors and parallel with one another, each in connection with and overlying at least a portion of the first and second active regions, respectively, of the first memory cell; and

second true and complementary bit lines formed in metal conductors and parallel with one another and with the first true and complementary bit lines, each of the second true and complementary bit lines in connection with and overlying at least a portion of the first and second active regions, respectively, of the second memory cell, the second true bit line disposed between the first true and complementary bit lines, and the first complementary bit line disposed between the second true and complementary bit lines;

a second bank of sense amplifiers associated with the second memory array block, each sense amplifier in the second bank of sense amplifiers associated with first true and complementary bit lines for a first column of memory cells, and with second true and complementary bit lines for a second column of memory cells, the first and second column of memory cells adjacent to one another and associated with first and second memory cells in a corresponding column of interleaved pairs of memory cells;

wherein the first and second memory arrays are disposed with adjacent edges with one another;

and wherein the second bank of sense amplifiers is disposed on a single side of the second memory array block, opposite the side of the first memory array block at which the first bank of sense amplifiers is disposed.

10. The memory array of claim 6, wherein the first polysilicon element serves as a word line for a first row of memory cells;

and wherein the second polysilicon element serves as a word line for a second row of memory cells adjacent to the first row of memory cells.

11. A non-volatile memory of the ferroelectric type, comprising:

address decoder circuitry, for driving one of a plurality of word lines responsive to a received memory address;

input/output circuitry, for receiving input data to be written to a selected memory cell and for presenting output data read from a selected memory cell;

a first memory array, comprised of two-transistor, two-capacitor ferroelectric memory cells arranged in rows and columns, and arranged as a plurality of pairs of adjacent memory cells, each pair of memory cells comprising;

a first memory cell associated with a first column, comprising;

first and second ferroelectric capacitors, each having a first plate coupled to a plate line, and having a second plate;

a first access transistor having a conduction path connected between the second plate of the first ferroelectric capacitor and a first bit line of the first column, the first access transistor connected to a word line; and

a second access transistor having a conduction path connected between the second plate of the first ferroelectric capacitor and a second bit line of the first column, the first access transistor connected to a word line; and

a second memory cell associated with a second column, comprising;

first and second ferroelectric capacitors, each having a first plate coupled to a plate line, and having a second plate;

a first access transistor having a conduction path connected between the second plate of the first ferroelectric capacitor and a first bit line of the second column, the first access transistor connected to a word line; and

a second access transistor having a conduction path connected between the second plate of the first ferroelectric capacitor and a second bit line of the second column, the first access transistor connected to a word line;

wherein the first and second bit lines of the first and second columns are parallel to one another;

wherein the first ferroelectric capacitor and the first access transistor of the second memory cell is disposed between the first and second ferroelectric capacitors of the first memory cell, so that the first bit line of the second column is disposed between the first and second bit lines of the first column;

and wherein the second ferroelectric capacitor and the second access transistor of the first memory cell is disposed between the first and second ferroelectric capacitors of the second memory cell, so that the second bit line of the first column is disposed between the first and second bit lines of the second column;

a first plurality of sense amplifiers, each associated with a pair of columns of memory cells in the first memory array and disposed on one side of the first memory array; and

a first plurality of multiplexers, each associated with one of the first plurality of sense amplifiers, each multiplexer having inputs receiving the first and second bit lines from each of its associated pair of columns, having outputs coupled to complementary inputs of its associated sense amplifier, and having select inputs receiving control signals corresponding to a column address from the address decoder circuitry, to selectively couple the first and second bit lines from one of its associated pair of columns, or the first and second bit lines from the other of its associated pair of columns, to the complementary inputs of its associated sense amplifier.

12. The memory of claim 11, further comprising:

a second memory array, comprised of two-transistor, two-capacitor ferroelectric memory cells arranged in rows and columns, and arranged as a plurality of pairs of adjacent memory cells, the second memory array disposed adjacent the first memory array on a side of the first memory array opposite the first plurality of sense amplifiers.

13. The memory of claim 12, wherein each pair of memory cells in the second memory array comprise:

a first memory cell associated with a first column, comprising;

first and second ferroelectric capacitors, each having a first plate coupled to a plate line, and having a second plate;

a first access transistor having a conduction path connected between the second plate of the first ferroelectric capacitor and a first bit line of the first column, the first access transistor connected to a word line; and

a second access transistor having a conduction path connected between the second plate of the first ferroelectric capacitor and a second bit line of the first column, the first access transistor connected to a word line; and

a second memory cell associated with a second column, comprising;

first and second ferroelectric capacitors, each having a first plate coupled to a plate line, and having a second plate;

a first access transistor having a conduction path connected between the second plate of the first ferroelectric capacitor and a first bit line of the second column, the first access transistor connected to a word line; and

a second access transistor having a conduction path connected between the second plate of the first ferroelectric capacitor and a second bit line of the second column, the first access transistor connected to a word line;

wherein the first and second bit lines of the first and second columns are parallel to one another;

wherein the first ferroelectric capacitor and the first access transistor of the second memory cell is disposed between the first and second ferroelectric capacitors of the first memory cell, so that the first bit line of the second column is disposed between the first and second bit lines of the first column;

and wherein the second ferroelectric capacitor and the second access transistor of the first memory cell is disposed between the first and second ferroelectric capacitors of the second memory cell, so that the second bit line of the first column is disposed between the first and second bit lines of the second column.

14. The memory of claim 13, further comprising:

a second plurality of sense amplifiers, each associated with a pair of columns of memory cells in the second memory array and disposed on one side of the second memory array; and

a second plurality of multiplexers, each associated with one of the second plurality of sense amplifiers, each multiplexer having inputs receiving the first and second bit lines from each of its associated pair of columns, having outputs coupled to complementary inputs of its associated sense amplifier, and having select inputs receiving control signals corresponding to a column address from the address decoder circuitry, to selectively couple the first and second bit lines from one of its associated pair of columns, or the first and second bit lines from the other of its associated pair of columns, to the complementary inputs of its associated sense amplifier.

wherein the second plurality of sense amplifiers is disposed adjacent a side of the second memory array opposite the first memory array.

15. The memory of claim 11, further comprising:

a plurality of word line drivers, each coupled to gate electrodes of the first and second access transistors of memory cells in a row of the first memory array;

wherein the first and second memory cells in each of the pairs of adjacent memory cells are associated with adjacent rows of memory cells in the first memory array.

16. The memory of claim 11, further comprising:

a plurality of plate line drivers, each coupled to the second plate of the first and second ferroelectric capacitors of memory cells in a row of the first memory array.

17. The memory of claim 11, wherein each of the first plurality of sense amplifiers is coupled to a local input/output line extending across the first memory array in a direction parallel with the first and second bit lines of each column;

and wherein, within each pair of memory cells, a local input/output line is disposed between one of the bit lines for the first column and one of the bit lines for the second column.

18. The memory of claim 17, wherein each of the first plurality of sense amplifiers is coupled to a complementary pair of local input/output lines extending across the array in a direction parallel with the bit lines of each column;

and wherein, within each pair of memory cells, a first one of a pair of local input/output lines is disposed between the first bit line for the first column and one of the bit lines for the second column, and a second one of the pair of local input/output lines is disposed between the first bit line for the second column and one of the bit lines for the first column.