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Interleaved Bit Line Architecture for 2T2C Ferroelectric Memories

  • US 20120307545A1
  • Filed: 06/01/2011
  • Published: 12/06/2012
  • Est. Priority Date: 06/01/2011
  • Status: Abandoned Application
First Claim
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1. A ferroelectric memory array comprised of two-transistor, two-capacitor ferroelectric memory cells arranged in rows and columns, and arranged as a plurality of pairs of adjacent memory cells, each pair of memory cells comprising:

  • a first memory cell associated with a first column, comprising;

    first and second ferroelectric capacitors, each having a first plate coupled to a plate line, and having a second plate;

    a first access transistor having a conduction path connected between the second plate of the first ferroelectric capacitor and a first bit line of the first column, the first access transistor connected to a word line; and

    a second access transistor having a conduction path connected between the second plate of the first ferroelectric capacitor and a second bit line of the first column, the first access transistor connected to a word line; and

    a second memory cell associated with a second column, comprising;

    first and second ferroelectric capacitors, each having a first plate coupled to a plate line, and having a second plate;

    a first access transistor having a conduction path connected between the second plate of the first ferroelectric capacitor and a first bit line of the second column, the first access transistor connected to a word line; and

    a second access transistor having a conduction path connected between the second plate of the first ferroelectric capacitor and a second bit line of the second column, the first access transistor connected to a word line;

    wherein the first and second bit lines of the first and second columns are parallel to one another;

    wherein the first ferroelectric capacitor and the first access transistor of the second memory cell is disposed between the first and second ferroelectric capacitors of the first memory cell, so that the first bit line of the second column is disposed between the first and second bit lines of the first column;

    and wherein the second ferroelectric capacitor and the second access transistor of the first memory cell is disposed between the first and second ferroelectric capacitors of the second memory cell, so that the second bit line of the first column is disposed between the first and second bit lines of the second column.

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