Interleaved Bit Line Architecture for 2T2C Ferroelectric Memories
First Claim
1. A ferroelectric memory array comprised of two-transistor, two-capacitor ferroelectric memory cells arranged in rows and columns, and arranged as a plurality of pairs of adjacent memory cells, each pair of memory cells comprising:
- a first memory cell associated with a first column, comprising;
first and second ferroelectric capacitors, each having a first plate coupled to a plate line, and having a second plate;
a first access transistor having a conduction path connected between the second plate of the first ferroelectric capacitor and a first bit line of the first column, the first access transistor connected to a word line; and
a second access transistor having a conduction path connected between the second plate of the first ferroelectric capacitor and a second bit line of the first column, the first access transistor connected to a word line; and
a second memory cell associated with a second column, comprising;
first and second ferroelectric capacitors, each having a first plate coupled to a plate line, and having a second plate;
a first access transistor having a conduction path connected between the second plate of the first ferroelectric capacitor and a first bit line of the second column, the first access transistor connected to a word line; and
a second access transistor having a conduction path connected between the second plate of the first ferroelectric capacitor and a second bit line of the second column, the first access transistor connected to a word line;
wherein the first and second bit lines of the first and second columns are parallel to one another;
wherein the first ferroelectric capacitor and the first access transistor of the second memory cell is disposed between the first and second ferroelectric capacitors of the first memory cell, so that the first bit line of the second column is disposed between the first and second bit lines of the first column;
and wherein the second ferroelectric capacitor and the second access transistor of the first memory cell is disposed between the first and second ferroelectric capacitors of the second memory cell, so that the second bit line of the first column is disposed between the first and second bit lines of the second column.
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Accused Products
Abstract
A ferroelectric memory with interleaved pairs of ferroelectric memory cells of the two-transistor, two-capacitor (2T2C) type. Each memory cell in a given pair is constructed as first and second portions, each portion including a transistor and a ferroelectric capacitor. Within each pair, a first portion of a second memory cell is physically located between the first and second portions of the first memory cell. As a result, complementary bit lines for adjacent columns are interleaved with one another. Each sense amplifier is associated with a multiplexer, so that the adjacent columns of the interleaved memory cells are supported by a single sense amplifier. Noise coupling among the bit lines is reduced, and the sense amplifiers can be placed along one side of the array, reducing the number of dummy cells required to eliminate edge cell effects.
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Citations
18 Claims
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1. A ferroelectric memory array comprised of two-transistor, two-capacitor ferroelectric memory cells arranged in rows and columns, and arranged as a plurality of pairs of adjacent memory cells, each pair of memory cells comprising:
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a first memory cell associated with a first column, comprising; first and second ferroelectric capacitors, each having a first plate coupled to a plate line, and having a second plate; a first access transistor having a conduction path connected between the second plate of the first ferroelectric capacitor and a first bit line of the first column, the first access transistor connected to a word line; and a second access transistor having a conduction path connected between the second plate of the first ferroelectric capacitor and a second bit line of the first column, the first access transistor connected to a word line; and a second memory cell associated with a second column, comprising; first and second ferroelectric capacitors, each having a first plate coupled to a plate line, and having a second plate; a first access transistor having a conduction path connected between the second plate of the first ferroelectric capacitor and a first bit line of the second column, the first access transistor connected to a word line; and a second access transistor having a conduction path connected between the second plate of the first ferroelectric capacitor and a second bit line of the second column, the first access transistor connected to a word line; wherein the first and second bit lines of the first and second columns are parallel to one another; wherein the first ferroelectric capacitor and the first access transistor of the second memory cell is disposed between the first and second ferroelectric capacitors of the first memory cell, so that the first bit line of the second column is disposed between the first and second bit lines of the first column; and wherein the second ferroelectric capacitor and the second access transistor of the first memory cell is disposed between the first and second ferroelectric capacitors of the second memory cell, so that the second bit line of the first column is disposed between the first and second bit lines of the second column. - View Dependent Claims (2, 3, 4, 5)
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6. An array of ferroelectric memory cells at a surface of a semiconductor body, the memory cells arranged in rows and columns within a first memory array block, each memory cell including two portions, each portion including a transistor and a ferroelectric capacitor, the memory cells arranged in interleaved pairs, each interleaved pair of memory cells comprising:
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first and second active regions for first and second portions, respectively, of a first memory cell; first and second active regions for first and second portions, respectively, of a second memory cell, the first portion of the second memory cell disposed at the surface between the first and second portions of the first memory cell of the pair; a first polysilicon element disposed over the first and second active regions of the first and second portions of the first memory cell, the first polysilicon element defining source/drain regions in each of the first and second active regions on either side thereof; a second polysilicon element disposed over the first and second active regions of the first and second portions of the second memory cell, the second polysilicon element defining source/drain regions in each of the first and second active regions on either side thereof; a first ferroelectric capacitor in connection with, and overlying at least a portion of, one of the source/drain regions of the first active region of the first memory cell; a second ferroelectric capacitor in connection with, and overlying at least a portion of, one of the source/drain regions of the second active region of the first memory cell; a third ferroelectric capacitor in connection with, and overlying at least a portion of, one of the source/drain regions of the first active region of the second memory cell, the third ferroelectric capacitor disposed between the first and second ferroelectric capacitors; a fourth ferroelectric capacitor in connection with, and overlying at least a portion of, one of the source/drain regions of the first active region of the second memory cell, so that the second ferroelectric capacitor is disposed between the third and fourth ferroelectric capacitors; first true and complementary bit lines formed in metal conductors and parallel with one another, each in connection with and overlying at least a portion of the first and second active regions, respectively, of the first memory cell; and second true and complementary bit lines formed in metal conductors and parallel with one another and with the first true and complementary bit lines, each of the second true and complementary bit lines in connection with and overlying at least a portion of the first and second active regions, respectively, of the second memory cell, the second true bit line disposed between the first true and complementary bit lines, and the first complementary bit line disposed between the second true and complementary bit lines. - View Dependent Claims (7, 8, 9, 10)
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11. A non-volatile memory of the ferroelectric type, comprising:
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address decoder circuitry, for driving one of a plurality of word lines responsive to a received memory address; input/output circuitry, for receiving input data to be written to a selected memory cell and for presenting output data read from a selected memory cell; a first memory array, comprised of two-transistor, two-capacitor ferroelectric memory cells arranged in rows and columns, and arranged as a plurality of pairs of adjacent memory cells, each pair of memory cells comprising; a first memory cell associated with a first column, comprising; first and second ferroelectric capacitors, each having a first plate coupled to a plate line, and having a second plate; a first access transistor having a conduction path connected between the second plate of the first ferroelectric capacitor and a first bit line of the first column, the first access transistor connected to a word line; and a second access transistor having a conduction path connected between the second plate of the first ferroelectric capacitor and a second bit line of the first column, the first access transistor connected to a word line; and a second memory cell associated with a second column, comprising; first and second ferroelectric capacitors, each having a first plate coupled to a plate line, and having a second plate; a first access transistor having a conduction path connected between the second plate of the first ferroelectric capacitor and a first bit line of the second column, the first access transistor connected to a word line; and a second access transistor having a conduction path connected between the second plate of the first ferroelectric capacitor and a second bit line of the second column, the first access transistor connected to a word line; wherein the first and second bit lines of the first and second columns are parallel to one another; wherein the first ferroelectric capacitor and the first access transistor of the second memory cell is disposed between the first and second ferroelectric capacitors of the first memory cell, so that the first bit line of the second column is disposed between the first and second bit lines of the first column; and wherein the second ferroelectric capacitor and the second access transistor of the first memory cell is disposed between the first and second ferroelectric capacitors of the second memory cell, so that the second bit line of the first column is disposed between the first and second bit lines of the second column; a first plurality of sense amplifiers, each associated with a pair of columns of memory cells in the first memory array and disposed on one side of the first memory array; and a first plurality of multiplexers, each associated with one of the first plurality of sense amplifiers, each multiplexer having inputs receiving the first and second bit lines from each of its associated pair of columns, having outputs coupled to complementary inputs of its associated sense amplifier, and having select inputs receiving control signals corresponding to a column address from the address decoder circuitry, to selectively couple the first and second bit lines from one of its associated pair of columns, or the first and second bit lines from the other of its associated pair of columns, to the complementary inputs of its associated sense amplifier. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18)
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Specification