SRAM READ and WRITE Assist Apparatus
First Claim
Patent Images
1. An apparatus comprising:
- a plurality of bit line tracking memory cells, each of which corresponds to a word line of a memory bank, wherein the plurality of bit line tracking memory cells are arranged in a column and coupled to a tracking bit line;
a bit line voltage tracking block coupled to the tracking bit line;
a READ assist timer coupled to the bit line voltage tracking block, wherein the READ assist timer generates a READ assist pulse; and
a READ assist unit configured to pull a voltage of a word line down to a lower level than a normal voltage of the word line when the READ assist pulse has a logic high state.
1 Assignment
0 Petitions
Accused Products
Abstract
A SRAM READ and WRITE assist apparatus comprises a bit line voltage tracking block, a READ assist timer, a READ assist unit, a WRITE assist unit a WRITE control unit. The bit line voltage tracking block detects a voltage on a tracking bit line coupled to a plurality of tracking memory cells. In response to the voltage drop on the tracking bit line, the READ assist timer generates a READ assist pulse. When the READ assist pulse has a logic high state, an activated word line is pulled down to a lower voltage. Such a lower voltage helps to improve the robustness of SRAM memory circuits so as to avoid READ and WRITE failures.
-
Citations
20 Claims
-
1. An apparatus comprising:
-
a plurality of bit line tracking memory cells, each of which corresponds to a word line of a memory bank, wherein the plurality of bit line tracking memory cells are arranged in a column and coupled to a tracking bit line; a bit line voltage tracking block coupled to the tracking bit line; a READ assist timer coupled to the bit line voltage tracking block, wherein the READ assist timer generates a READ assist pulse; and a READ assist unit configured to pull a voltage of a word line down to a lower level than a normal voltage of the word line when the READ assist pulse has a logic high state. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
-
-
9. A system comprising:
-
a plurality of tracking memory cells arranged in a column; a memory bank having a plurality of memory cells arranged in a plurality of rows, each of which is coupled to a word line; and a READ and WRITE assist apparatus comprising; a bit line voltage tracking block configured to detect a voltage on a tracking bit line coupled to the plurality of tracking memory cells; a READ assist timer coupled to the bit line voltage tracking block, wherein the READ assist timer generates a READ assist pulse; a READ assist unit configured to pull a voltage of a word line down to a lower level than a normal voltage of the word line when the READ assist pulse has a logic high state; a WRITE assist unit configured to generate a WRITE assist pulse in response to the READ assist pulse; and a WRITE control unit configured to pull an operating voltage of the memory bank down to a lower level than a normal operating voltage of the memory bank when the WRITE assist pulse has a logic high state. - View Dependent Claims (10, 11, 12, 13, 14)
-
-
15. A method comprising:
-
performing a READ “
0”
operation at a plurality of tracking memory cells coupled to a tracking bit line;detecting a voltage on the tracking bit line; generating a READ assist pulse; and terminating the READ assist pulse when the voltage on the tracking bit line drops below a predetermined value. - View Dependent Claims (16, 17, 18, 19, 20)
-
Specification