Semiconductor Component and Method for Producing a Semiconductor Component

• US 20120309147A1
• Filed: 08/14/2012
• Published: 12/06/2012
• Est. Priority Date: 12/22/2009
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Wood, Andrew, Zelsacher, Rudolf, Zundel, Markus
• Granted Patent: US 9,171,950 B2
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0882 Disposition
• CPC Class Codes: H01L 29/0886 Shape
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor component is produced by forming a trench in a semiconductor region. The trench has an upper trench region and a lower trench region. The upper trench region is wider than the lower trench region such that a step is formed in the semiconductor region. A dopant is introduced into the step to form a locally delimited dopant region in the semiconductor region.

Claims

1. A method for producing a semiconductor component, the method comprising:

forming a trench in a semiconductor region, the trench having an upper trench region and a lower trench region, the upper trench region being wider than the lower trench region such that a step is formed in the semiconductor region; and

introducing a dopant into the step to form a locally delimited dopant region in the semiconductor region.

2. The method according to claim 1, wherein the trench is firstly produced with a first width, sidewalls of the lower trench region are covered with a protective layer with the upper trench region not covered by the protective layer, and the upper trench region not covered by the protective layer is widened to a second width greater than the first width.

3. The method according to claim 2, wherein sidewalls of the upper trench region are firstly converted into a sacrificial layer, and the sacrificial layer is subsequently removed selectively from the semiconductor region to widen the upper trench region to the second width greater than the first width.

4. The method according to claim 2, wherein the semiconductor region is removed adjacent the upper trench region not covered by the protective layer to widen the upper trench region to the second width greater than the first width

5. The method according to claim 1, wherein the trench is produced so that firstly only the upper trench region is produced with a first width, side walls of the upper trench region are covered with a protective layer and the lower trench region is subsequently produced at a non-protected bottom of the upper trench region further into the semiconductor region with a second width smaller than the first width.

6. The method according to claim 1, wherein the dopant is implanted into the semiconductor region.

7. The method according to claim 6, wherein the dopant is implanted into the semiconductor region with an angle in the range of 0°

to 7°

with respect to a main surface normal of the semiconductor region.

8. A method for producing a semiconductor component, the method comprising:

forming at least one field effect transistor along a trench extending vertically downward from a horizontal top surface in a semiconductor region, the at least one field effect transistor having a source region of a first conductivity type along the trench and extending downward from the horizontal top surface, a drain region of the first conductivity type, and a body region of a second conductivity type disposed between the source region and the drain region in the semiconductor region so as to form a first generally horizontal junction between the source region and the body region and a second generally horizontal junction between the body region and the drain region, the first and second generally horizontal junctions having a first vertical depth and a second vertical depth, respectively, relative to the horizontal top surface;

forming a gate electrode in the trench along the body region, the gate electrode arranged in a manner isolated from the body region by a gate dielectric and extending vertically from an uppermost surface of the gate electrode, at a third vertical depth relative to the horizontal top surface, to a lower-most surface of the gate electrode, at a fourth vertical depth relative to the horizontal top surface, such that either the third vertical depth is greater than the first vertical depth or the fourth vertical depth is less than the second vertical, or both; and

forming a first locally delimited dopant region of the first conductivity type in the semiconductor region, the first locally delimited dopant region extending either downward from the first generally horizontal junction between the source region and the body region to below the third vertical depth, or extending upward from the second generally horizontal junction between the drain region and the body region to above the fourth depth, so that a part of the first dopant region extends vertically in the body region to bridge a gap in the body region between the first vertical depth and the third vertical depth or a gap in the body region between the second vertical depth and the fourth vertical depth.

9. The method according to claim 8, wherein the first locally delimited dopant region extends downward from the first generally horizontal junction between the source region and the body region to below the third vertical depth, so as to bridge a first gap in the body region between the first vertical depth and the third vertical depth, the semiconductor component further comprising a second locally delimited dopant region extending upward from the second generally horizontal junction between the drain region and the body region to above the fourth depth, so that a part of the first dopant region extends vertically in the body region to bridge a second gap in the body region between the second vertical depth and the fourth vertical depth.

10. The method according to claim 8, wherein the trench is formed with a wide upper trench region and a narrower lower trench region so that a step is formed in the semiconductor region.

11. The method according to claim 8, wherein the gate dielectric and the gate electrode are formed in a first region of the trench, the method further comprising:

forming a field plate in a second region of the trench along the drain region; and

isolating the field plate from the drain region by a field plate dielectric.

12. The method according to claim 11, further comprising isolating the gate electrode from the field plate by a dielectric.