MULTI-LAYER TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTOR (ADC)

• US 20120309337A1
• Filed: 05/31/2012
• Published: 12/06/2012
• Est. Priority Date: 06/03/2011
• Status: Active Grant

• Current Assignee: Entropic Communications, LLC (FIG LLC (d/b/a Fortress Investment Group LLC))
• Original Assignee: Maxlinear Incorporated
• Inventors: Fogleman, Eric, Zhu, Jianyu, Peng, Sheng-Yu, Chandler, Rodney, Tiwari, Pawan, Bhatia, Rahul
• Granted Patent: US 8,611,483 B2
• Time in Patent Office: Days
• US Class Current: 455/341
• CPC Class Codes: H03M 1/1215 using time-division multiplexing
• CPC Class Codes: H03M 1/1245 Details of sampling arrangements or methods
• CPC Class Codes: H04L 7/0334 Processing of samples having at least three levels, e.g. soft decisions

Abstract

A radio frequency (RF) receiver may comprise a first sampling module that is operable to sample in a first level at a particular main sampling rate; a plurality of second-level sampling modules, wherein each of the plurality of second-level sampling modules is operable to sample in a second level, an output of the first level, at a second sampling rate that is reduced compared to the main sampling rate; and a plurality of third-level modules, each comprising a plurality of third-stage sampling sub-modules that are operable to sample at a third sampling rate that is reduced compared to the second sampling rate, and a plurality of corresponding analog-to-digital conversion (ADC) sub-modules.

Claims

1. A method, comprising:

in an electronic device;

sampling in a first level, at a particular main sampling rate, an input RF signal;

sampling in a second level an output of said first level, via a plurality of second-level branches, wherein each of said plurality of second-level branches samples at a second sampling rate that is reduced compared to said main sampling rate; and

processing in a third level, each output of said plurality of second-level branches via a corresponding one of a plurality of third-level branches, wherein each of said plurality of third-level branches comprises a plurality of sub-branches, and each of said plurality of sub-branches;

samples at a third sampling rate that is reduced compared to said second sampling rate; and

applies analog-to-digital conversion (ADC).

2. The method according to claim 1, comprising applying low-noise amplification to said input RF signal in said first level.

3. The method according to claim 1, comprising setting said second sampling rate and/or said third sampling rate by configuring clock signals driving said plurality of second-level branches and/or said plurality of third-level branches based on and/or relative to a clock signal applied in said first level.

4. The method according to claim 3, comprising reducing, based on number of said plurality of second-level branches, a frequency of each clock signal driving said plurality of second-level branches relative to a frequency of said clock signal applied in said first level.

5. The method according to claim 4, comprising, for each one of said plurality of third-level branches, reducing a frequency of each clock signal driving each of plurality of sub-branches of said one of said plurality of third-level branches, relative to a frequency of a clock signal driving a corresponding one of said plurality of second-level branches, based on a number of said plurality of sub-branches.

6. The method according to claim 1, comprising holding output signals of each of said first level, said plurality of second-level branches, and said third-level sub-branches of said plurality of third-level branches, during non-read periods as determined based on an applicable sampling rate.

7. The method according to claim 6, comprising holding said output signals using grounding logic.

8. A system, comprising:

one or more circuits for use in an electronic device, the one or more circuits being operable to;

sample in a first level, at a particular main sampling rate, an input RF signal;

sample in a second level an output of said first level, via a plurality of second-level branches, wherein each of said plurality of second-level branches samples at a second sampling rate that is reduced compared to said main sampling rate; and

processing in a third level, each output of said plurality of second-level branches via a corresponding one of a plurality of third-level branches, wherein each of said plurality of third-level branches comprises a plurality of sub-branches, and each sub-branch;

samples at a third sampling rate that is reduced compared to said second sampling rate; and

applies analog-to-digital conversion (ADC).

9. The system according to claim 8, wherein said one or more circuits are operable to apply low-noise amplification to said input RF signal in said first level.

10. The system according to claim 8, wherein said one or more circuits are operable to set said second sampling rate and/or said third sampling rate by configuring clock signals driving said plurality of second-level branches and/or said plurality of third-level branches based on and/or relative to a clock signal applied in said first level.

11. The system according to claim 10, wherein said one or more circuits are operable to reduce, based on number of said plurality of second-level branches, a frequency of each clock signal driving said plurality of second-level branches relative to a frequency of said clock signal applied in said first level.

12. The system according to claim 11, wherein said one or more circuits are operable to reduce, for each one of said plurality of third-level branches, frequency of each clock signal driving each of a plurality of sub-branches of said one of said plurality of third-level branches, relative to a frequency of a clock signal driving a corresponding one of said plurality of second-level branches, based on a number of said plurality of sub-branches.

13. The system according to claim 8, wherein said one or more circuits are operable to hold output signals of each of said first level, said plurality of second-level branches, and all third-level sub-branches during non-read periods as determined based on an applicable sampling rate.

14. The system according to claim 13, wherein said one or more circuits are operable to hold said output signals based on grounding logic.

15. A system, comprising:

a radio frequency (RF) receiver implemented on a single chip, the RF receiver comprising;

a first sampling module that is operable to sample in a first level, an input RF signal, at a particular main sampling rate;

a plurality of second-level sampling modules, wherein each of said plurality of second-level sampling modules is operable to sample in a second level, an output of said first level, at a second sampling rate that is reduced compared to said main sampling rate;

a plurality of third-level sampling modules, wherein;

each of said plurality of third-level sampling modules is operable to samples in a third level, at a third sampling rate that is reduced compared to said second sampling rate; and

said plurality of third-level sampling modules is configured into a plurality of sub-sets, each of said plurality of sub-sets corresponding to one of said plurality of second-level sampling modules; and

a plurality of third-level analog-to-digital conversion (ADC) modules, wherein each of said ADC modulates is associated with a particular one of said plurality of third-level sampling modules.

16. The system according to claim 15, wherein said RF receiver comprises a low-noise amplifier for amplifying said input RF signal in said first level.

17. The system according to claim 15, wherein said RF receiver comprises a buffer for buffering an output of said first level and/or a plurality of second-level buffers, wherein each of said plurality of second-level buffers is operable to buffer an output of a corresponding one of said plurality of second-level sampling modules.

18. The system according to claim 15, wherein said RF receiver is operable to set said second sampling rate and/or said third sampling rate by configuring clock signals driving said plurality of second-level sampling modules and/or said plurality of third-level sampling modules, relative to a clock signal driving said first sampling module.

19. The system according to claim 18, wherein said RF receiver is operable to:

reduce, relative to a frequency of said clock signal driving said first sampling module, a frequency of each of clock signals driving said plurality of second-level sampling modules, based on a number of said plurality of second-level sampling modules; and

reduce, for each one of said plurality of third-level sampling modules, a frequency of a clock signal driving said one of said plurality of third-level sampling modules, relative to frequency of a clock signal driving one of said plurality of second-level branches associated with one of said plurality of sub-sets comprising said one of said plurality of third-level sampling modules, based on said one of said plurality of sub-sets.

20. The system according to claim 15, wherein said RF receiver is operable to perform at least some of digital processing of outputs of said plurality of third-level ADC modules, said digital processing comprising filtering and decoding to extract desired signals or data.