COMPUTER BUS WITH ENHANCED FUNCTIONALITY
First Claim
Patent Images
1. A method for computing, comprising:
- connecting a host device to a peripheral device via a bus that is physically configured in accordance with a predefined standard and comprises multiple connection pins that are specified by the standard, including a plurality of ground pins; and
using at least one pin selected from among the pins on the bus that are specified as the ground pins in order to indicate to the peripheral device that the host device has an extended operational capability.
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Accused Products
Abstract
A method for computing includes connecting a host device to a peripheral device via a bus that is physically configured in accordance with a predefined standard and includes multiple connection pins that are specified by the standard, including a plurality of ground pins. At least one pin, selected from among the pins on the bus that are specified as the ground pins, is used in order to indicate to the peripheral device that the host device has an extended operational capability.
21 Citations
36 Claims
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1. A method for computing, comprising:
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connecting a host device to a peripheral device via a bus that is physically configured in accordance with a predefined standard and comprises multiple connection pins that are specified by the standard, including a plurality of ground pins; and using at least one pin selected from among the pins on the bus that are specified as the ground pins in order to indicate to the peripheral device that the host device has an extended operational capability. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method for computing, comprising:
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connecting a peripheral device to a host device to via a bus that is physically configured in accordance with a predefined standard and comprises multiple connection pins that are specified by the standard, including a plurality of ground pins; detecting in the peripheral device an extended operational capability of the host device by sensing an electrical level of at least one pin selected from among the pins on the bus that are specified as the ground pins; and operating the peripheral device in accordance with the extended operational capability. - View Dependent Claims (14, 15, 16, 17, 18)
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19. A computing device, comprising:
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a host processor; and a bus, which is coupled to the host processor and which is physically configured in accordance with a predefined standard, which specifies multiple connection pins of the bus, including a plurality of ground pins, the bus comprising at least one pin, selected from among the pins on the bus that are specified as the ground pins, that is used to indicate to a peripheral device connected to the bus that the computing device has an extended operational capability. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30)
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31. A computing device, comprising:
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a bus interface, which is configured to connect a the computing device to a host device via a bus that is physically configured in accordance with a predefined standard and comprises multiple connection pins that are specified by the standard, including a plurality of ground pins, and which comprises a sensing circuit, which is coupled to detect an electrical level of at least one pin selected from among the pins on the bus that are specified as the ground pin and to output a signal in response to the electrical level; and a controller, which is coupled to receive the signal from the sensing circuit and is configured to cause the computing device, in response to the signal, to operate in accordance with an extended operational capability of the host device that is indicated by the floating of the at least one pin. - View Dependent Claims (32, 33, 34, 35, 36)
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Specification