APPARATUS INCLUDING MEMORY SYSTEM CONTROLLERS AND RELATED METHODS

• US 20120311232A1
• Filed: 05/31/2011
• Published: 12/06/2012
• Est. Priority Date: 05/31/2011
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Porterfield, Kent A.
• Granted Patent: US 9,514,838 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Memory controllers can include a switch and non-volatile memory control circuitry including channel control circuits coupled to the switch. The channel control circuits can coupled to logical units including blocks. Volatile memory and memory management circuitry including local memory can be coupled to the switch. The memory management circuitry can be configured to store health and status information for each of the blocks in a block table in the volatile memory, store a candidate block table that identifies a candidate block for a particular operation based on criteria in the local memory, update the health and status information for a particular block in the block table, compare the updated health and status information for the particular block with the candidate block according to the criteria, and update the candidate block table to identify the particular block in response to the comparison indicating that the particular block better satisfies the criteria.

Claims

1. An apparatus, comprising:

a switch;

non-volatile memory control circuitry coupled to the switch and including a plurality of channel control circuits, wherein each of the plurality of channel control circuits is configured to be coupled to a number of logical units (LUNs), wherein each of the number of LUNs includes a plurality of blocks;

volatile memory coupled to the switch; and

memory management circuitry coupled to the switch and including local memory, wherein the memory management circuitry is configured to;

store health and status information for each of the plurality of blocks in a block table in the volatile memory;

store a candidate block table in the local memory, wherein the candidate block table identifies a candidate block for a particular operation based on a number of criteria for the particular operation;

update the health and status information for a particular one of the plurality of blocks in the block table in the volatile memory; and

compare the updated health and status information for the particular block with the candidate block according to the number of criteria; and

update the candidate block table to identify the particular block at least partially in response to the comparison indicating that the particular block better satisfies the number of criteria.

2. The apparatus of claim 1, wherein the candidate block table identifies a candidate block for the particular operation selected from a group of operations including a host write, a wear leveling read, a wear leveling write, and an erase.

3. The apparatus of claim 1, wherein the memory management circuitry is configured to update the health and status information for the particular block in the block table in the volatile memory at least partially in response to one of a write, an erase, or an error event for the particular block.

4. The apparatus of claim 1, wherein the memory management circuitry is configured to update the candidate block table to identify the particular block on a same clock cycle during which the health and status information for the particular block is updated in the volatile memory.

5. The apparatus of claim 1, wherein the memory management circuitry is configured to compare the updated health and status information for each of the plurality of blocks in the block table in the volatile memory with the candidate block according to the number of criteria independent of a write, an erase, or an error event for any of the plurality of blocks.

6. The apparatus of claim 5, wherein the memory management circuitry is configured to cease comparing the health and status information independent of a write, an erase, or an error event after each of the plurality of blocks has been compared.

7. The apparatus of claim 1, wherein the memory management circuitry is configured to:

store logical to physical address translations in a logical block address (LBA) table in the volatile memory;

retrieve a first physical address corresponding to a logical address for a particular block of the plurality of blocks from the block table prior to information being read from the particular block during a wear leveling operation on the particular block;

retrieve a second physical address corresponding to the logical address from the LBA table after the information is written to a different one of the plurality of blocks during the wear leveling operation; and

update the LBA table with a third physical address corresponding to the different block at least partially in response to the second physical address being equal to the first physical address.

8. The apparatus of claim 7, wherein the memory management control circuitry is configured to invalidate the wear leveling operation at least partially in response to the second physical address being different than the first physical address.

9. A method, comprising:

storing health and status information for each of a plurality of blocks in a block table in volatile memory;

storing a candidate block table in local memory, wherein the candidate block table identifies a candidate block for a particular operation based on a number of criteria for the particular operation;

updating the health and status information for a particular one of the plurality of blocks in the block table in the volatile memory; and

comparing the updated health and status information for the particular block with the candidate block according to the number of criteria; and

updating the candidate block table to identify the particular block at least partially in response to the comparison indicating that the particular block better satisfies the number of criteria.

10. The method of claim 9, wherein the particular operation is selected from a group of operations including a host write, a wear leveling read, a wear leveling write, and an erase.

11. The method of claim 9, wherein updating the health and status information for the particular block in the block table in the volatile memory includes updating at least partially in response to one of a write, an erase, or an error event for the particular block.

12. The method of claim 9, wherein updating the candidate block table to identify the particular block comprises updating the candidate block table on a same clock cycle during which the health and status information for the particular block is updated in the volatile memory.

13. The method of claim 9, wherein comparing the updated health and status information for the particular block with the candidate block according to the number of criteria comprises comparing independent of a write, an erase, or an error event for any of the plurality of blocks.

14. The method of claim 13, wherein the method includes ceasing comparing the health and status information independent of a write, an erase, or an error event after each of the plurality of blocks has been compared.

15. The method of claim 9, wherein the method includes:

storing logical to physical address translations in a logical block address (LBA) table in the volatile memory;

retrieving a first physical address corresponding to a logical address for a particular block of the plurality of blocks from the block table prior to information being read from the particular block during a wear leveling operation on the particular block;

retrieving a second physical address corresponding to the logical address from the LBA table after the information is written to a different one of the plurality of blocks during the wear leveling operation; and

updating the LBA table with a third physical address corresponding to the different block at least partially in response to the second physical address being equal to the first physical address.

16. The method of claim 15, wherein the method includes invalidating the wear leveling operation at least partially in response to the second physical address being different than the first physical address.

17. A method, comprising:

storing logical to physical address translations in a logical block address (LBA) table in volatile memory;

retrieving a first physical address corresponding to a logical address for a particular block of a plurality of blocks from a block table prior to information being read from the particular block during a wear leveling operation on the particular block;

retrieving a second physical address corresponding to the logical address from the LBA table after the information is written to a different one of the plurality of blocks during the wear leveling operation; and

invalidating the wear leveling operation at least partially in response to the second physical address being different than the first physical address.

18. The method of claim 17, wherein the method includes updating the LBA table with a third physical address corresponding to the different block at least partially in response to the second physical address being equal to the first physical address.

19. An apparatus, comprising:

a switch;

non-volatile memory control circuitry coupled to the switch and including a plurality of channel control circuits, wherein each of the plurality of channel control circuits is configured to be coupled to a number of logical units (LUNs), wherein each of the number of LUNs includes a plurality of blocks;

volatile memory coupled to the switch; and

memory management circuitry coupled to the switch and including local memory, wherein the memory management circuitry is configured to;

store logical to physical address translations in a logical block address (LBA) table in the volatile memory;

retrieve a first physical address corresponding to a logical address for a particular block of the plurality of blocks from the block table prior to information being read from the particular block during a wear leveling operation on the particular block;

retrieve a second physical address corresponding to the logical address from the LBA table after the information is written to a different one of the plurality of blocks during the wear leveling operation; and

update the LBA table with a third physical address corresponding to the different block at least partially in response to the second physical address being equal to the first physical address.

20. The apparatus of claim 19, wherein the memory management control circuitry is configured to invalidate the wear leveling operation at least partially in response to the second physical address being different than the first physical address.