SEMICONDUCTOR STORAGE DEVICE WITH VOLATILE AND NONVOLATILE MEMORIES

• US 20120311245A1
• Filed: 08/09/2012
• Published: 12/06/2012
• Est. Priority Date: 12/28/2007
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Hidenori Matsuzaki, Hirokuni Yano, Kazuya Kitsunai, Shigehiro Asano, Shinichi Kanno, Toshikatsu Hida
• Inventors: YANO, Hirokuni, Kanno, Shinichi, Hida, Toshikatsu, Matsuzaki, Hidenori, Kitsunai, Kazuya, Asano, Shigehiro
• Granted Patent: US 8,782,331 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7209 Validity control, e.g. using flags, time stamps or sequence numbers
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0631 by allocating resources to storage systems
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits

Abstract

A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.

Claims

1. A solid state drive comprising:

an interface controller configured to receive data provided from an external host apparatus;

a nonvolatile memory configured to store data transmitted from the interface controller in at least one of a plurality of blocks, each one of the plurality of blocks being a unit of data erasing; and

a drive controller coupled with the interface controller and the nonvolatile memory via at least one internal bus, the drive controller is configured to;

allocate a plurality of blocks to a first memory area, the plurality of blocks allocated to the first memory area including SLC (Single Level Cell) blocks;

relocate at least one of the SLC blocks to a second memory area from the first memory area, a plurality of blocks allocated to the second memory area including SLC blocks and MLC (Multi Level Cell) blocks;

copy valid data stored in the SLC blocks to one of the MLC blocks, within the second memory area, when a predetermined condition is satisfied; and

de-allocate at least one of the SLC blocks in which no valid data is stored from the second memory area, after copying the valid data stored in the SLC blocks.

2. The solid state drive according to claim 1, wherein the SLC blocks include pseudo SLC blocks.

3. The solid state drive according to claim 1, wherein a programming time for an SLC block is shorter than that for an MLC block.

4. The solid state drive according to claim 1, wherein a capacity of an SLC block is smaller than that of an MLC block.

5. The solid state drive according to claim 1, wherein the drive controller is configured to write data, transmitted from the interface controller, to the first memory area.

6. The solid state drive according to claim 5, wherein the drive controller is configured to invalidate data, having the same logical address as the data newly written to the first memory area, stored in the first or second memory area.

7. The solid state drive according to claim 6, wherein the drive controller is configured to manage the SLC blocks allocated to the first memory area with FIFO (First In First Out) data structure sorted by an allocation order.

8. The solid state drive according to claim 7, wherein the drive controller is configured to, when writing data to the first memory area, allocate a new SLC block to the first memory area at an input side of the FIFO data structure.

9. The solid state drive according to claim 8, wherein the drive controller is configured to relocate an SLC block having an oldest allocation order at an output side of the FIFO data structure to the second memory area.

10. The solid state drive according to claim 1, wherein a number of blocks allocatable to the first memory area has an upper limit.

11. The solid state drive according to claim 10, wherein the drive controller is configured to relocate at least one of the SLC blocks to the second memory area when a number of the SLC blocks allocated to the first memory area exceeds the upper limit.

12. The solid state drive according to claim 1, wherein the first condition is satisfied when a number of the SLC and MLC blocks allocated to the second memory area exceeds a threshold.

13. The solid state drive according to claim 1, wherein the nonvolatile memory is a NAND type flash memory.

14. The solid state drive according to claim 1, wherein the nonvolatile memory includes a plurality of memory chips.

15. A method of controlling a solid state drive, the solid state drive including a nonvolatile memory, the method comprising:

receiving data provided from an external host apparatus;

storing data in at least one of a plurality of blocks included in the nonvolatile memory, each one of the plurality of blocks being a unit of data erasing;

allocating a plurality of blocks to a first memory area, the plurality of blocks allocated to the first memory area including SLC (Single Level Cell) blocks;

relocating at least one of the SLC blocks to a second memory area from the first memory area, a plurality of blocks allocated to the second memory area including SLC blocks and MLC (Multi Level Cell) blocks;

copying valid data stored in the SLC blocks to one of the MLC blocks, within the second memory area, when a predetermined condition is satisfied; and

de-allocating at least one of the SLC blocks in which no valid data is stored from the second memory area, after copying the valid data stored in the SLC blocks.

16. The method according to claim 15, wherein the SLC blocks include pseudo SLC blocks.

17. The method according to claim 15, wherein a programming time for an SLC block is shorter than that for an MLC block.

18. The method according to claim 15, wherein a capacity of an SLC block is smaller than that of an MLC block.

19. The method according to claim 15, further comprising:

writing data, received from the external host apparatus, to the first memory area.

20. The method according to claim 19, further comprising:

invalidating data, having the same logical address as the data newly written to the first memory area, stored in the first or second memory area.