CACHE LINE LOCK FOR PROVIDING DYNAMIC SPARING

• US 20120311248A1
• Filed: 06/03/2011
• Published: 12/06/2012
• Est. Priority Date: 06/03/2011
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Goodman, Benjiman L.
• Application Number:
  US13/152,861
• Publication Number:
  US 20120311248A1
• Time in Patent Office: Days
• US Class Current: 711/105
• CPC Class Codes: G06F 12/126 with special data handling, e.g. priority of data or instructions, handling errors or pinning

Abstract

A system that includes a memory, a cache, a purge mechanism, and a memory interface mechanism. The memory includes a failing memory element at a failing memory location. The cache is configured for storing corrected contents of the failing memory element in a locked state, with the corrected contents stored in a first cache line. The purge mechanism is configured for selecting and removing cache lines that are not in the locked state from the cache to make room for new cache allocations. The memory interface mechanism is configured for receiving a request to access the failing memory location, determining that corrected contents of the failing memory location are stored in first cache line in the cache, and accessing the first cache line in the cache.

Claims

1. A system comprising:

a memory comprising a failing memory element at a failing memory location;

a cache configured for storing corrected contents of the failing memory element in a locked state, the corrected contents stored in a first cache line;

a purge mechanism configured for selecting and removing cache lines that are not in the locked state from the cache to make room for new cache allocations; and

a memory interface mechanism configured for;

receiving a request to access the failing memory location;

determining that corrected contents of the failing memory location are stored in first cache line in the cache; and

accessing the first cache line in the cache.

2. The system of claim 1, wherein the memory is a dynamic random access memory (DRAM).

3. The system of claim 1, wherein the selecting is responsive to a least recently used (LRU) algorithm.

4. The system of claim 1, wherein the removing comprises assigning an invalid state to the cache lines.

5. The system of claim 1, wherein once a cache line is in the locked state, the cache line remains in the locked state in the cache until it is updated by a control program that has authorization to remove the locked state from the cache line.

6. The system of claim 1, wherein the cache comprises multiple cache hierarchies and the first cache line is located in any of the multiple cache hierarchies.

7. The system of claim 1, wherein the system is a multiple processor system and a plurality of processors share the cache.

8. A method comprising:

identifying a failing memory element at a failing memory location in a memory in a computer system;

storing corrected contents of the failing memory element in a locked state in a first line of a cache;

performing a purge process that comprises selecting and removing cache lines that are not in the locked state from the cache; and

servicing data access requests, the servicing comprising;

receiving a request to access the failing memory location;

determining that corrected contents of the failing memory location are stored in first cache line in the cache; and

accessing the first cache line in the cache.

9. The method of claim 8, wherein the memory is a dynamic random access memory (DRAM).

10. The method of claim 8, wherein the selecting is responsive to a least recently used (LRU) algorithm.

11. The method of claim 8, wherein the removing comprises assigning an invalid state to the cache lines.

12. The method of claim 8, wherein once a cache line is in the locked state, the cache line remains in the locked state in the cache until it is updated by a control program that has authorization to remove the locked state from the cache line.

13. The method of claim 8, wherein the cache comprises multiple cache hierarchies and the first cache line is located in any of the multiple cache hierarchies.

14. The method of claim 8, wherein the computer system is a multiple processor system and a plurality of processors share the cache.

15. A computer program product comprising:

a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising;

identifying a failing memory element at a failing memory location in a memory in a computer system;

storing corrected contents of the failing memory element in a locked state in a first line of a cache;

performing a purge process that comprises selecting and removing cache lines that are not in the locked state from the cache; and

servicing data access requests, the servicing comprising;

receiving a request to access the failing memory location;

determining that corrected contents of the failing memory location are stored in first cache line in the cache; and

accessing the first cache line in the cache.

16. The computer program product of claim 15, wherein the memory is a dynamic random access memory (DRAM).

17. The computer program product of claim 15, wherein the selecting is responsive to a least recently used (LRU) algorithm.

18. The computer program product of claim 15, wherein the removing comprises assigning an invalid state to the cache lines.

19. The computer program product of claim 15, wherein once a cache line is in the locked state, the cache line remains in the locked state in the cache until it is updated by a control program that has authorization to remove the locked state from the cache line.

20. The computer program product of claim 15, wherein the cache comprises multiple cache hierarchies and the first cache line is located in any of the multiple cache hierarchies.