MEMORY CELL PRESETTING FOR IMPROVED MEMORY PERFORMANCE
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Abstract
Memory cell presetting for improved performance including a system that includes a memory, a cache, and a memory controller. The memory includes memory lines made up of memory cells. The cache includes cache lines that correspond to a subset of the memory lines. The memory controller is in communication with the memory and the cache. The memory controller is configured to perform a method that includes scheduling a request to set memory cells of a memory line to a common specified state in response to a cache line attaining a dirty state.
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Citations
24 Claims
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1-18. -18. (canceled)
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19. A system comprising:
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a memory comprising memory lines, each memory line comprising a plurality of memory cells; a cache comprising cache lines corresponding to a subset of the memory lines; and a memory controller in communication with the memory and the cache, the memory controller configured to perform a method that comprises scheduling a request to set memory cells of a memory line to a common specified state in response to a cache line attaining a dirty state. - View Dependent Claims (20, 21, 22, 23)
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24-25. -25. (canceled)
Specification