DYNAMIC MEMORY CACHE SIZE ADJUSTMENT IN A MEMORY DEVICE

• US 20120311293A1
• Filed: 05/31/2011
• Published: 12/06/2012
• Est. Priority Date: 05/31/2011
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Nemazie, Siamack, Iman, Berhanu, Benson, William E., Tabrizi, Farshid, Shah, Ruchir, George, Michael
• Granted Patent: US 8,886,911 B2
• Time in Patent Office: Days
• US Class Current: 711/171
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0871 Allocation or management of cache space
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/222 Non-volatile memory
• CPC Class Codes: G06F 2212/224 Disk storage
• CPC Class Codes: G06F 2212/601 Reconfiguration of cache memory
• CPC Class Codes: G06F 2212/6046 Using a specific cache allocation policy other than replacement policy
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7206 Reconfiguration of flash memory system
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory

Abstract

Methods for dynamic memory cache size adjustment, enabling dynamic memory cache size adjustment, memory devices, and memory systems are disclosed. One such method for dynamic memory cache size adjustment determines available memory space in a memory array and adjusts a size of a memory cache in the memory array responsive to the available memory space.

Claims

1. A method for dynamic memory cache size adjustment, the method comprising:

determining available memory space in a memory array; and

adjusting a size of a memory cache in the memory array responsive to the available memory space.

2. The method of claim 1 and further including:

determining if a file system of a memory device that includes the memory array is supported; and

enabling dynamic memory cache size adjustment if the particular file system is supported.

3. The method of claim 1 wherein the available memory space is one of erased memory that is not targeted for use or unerased memory that stores data that is not valid.

4. The method of claim 1 wherein the size of the memory cache is a percentage of the available memory space.

5. The method of claim 4 and further including dynamically adjusting the percentage.

6. The method of claim 4 wherein the percentage of the available memory space is a fixed percentage of the available memory space.

7. The method of claim 4 wherein the percentage of the available memory space is a variable percentage of the available memory space.

8. The method of claim 7 wherein the variable percentage of the available memory space increases when the available memory space increases over a particular time period.

9. The method of claim 7 wherein the variable percentage of the available memory space decreases when the available memory space decreases over a particular time period.

10. The method of claim 1 wherein adjusting a size comprises allocating a first number of blocks of the memory array for use as the memory cache and allocating a second number of blocks of the memory array for use as main memory.

11. The method of claim 10 wherein allocating a first number of blocks includes allocating a block previously allocated for use as part of the main memory for use as part of the memory cache.

12. The method of claim 10 wherein memory cells in a block allocated for use as part of the main memory are programmed as MLC cells, and wherein memory cells in a block allocated for use as part of the memory cache are programmed as SLC cells.

13. The method of claim 10 wherein allocating a block previously allocated for use as part of the main memory for use as part of the memory cache comprises switching between programming memory cells of the block as MLC cells to programming the memory cells of the block as SLC cells.

14. The method of claim 1 wherein adjusting comprises dynamically adjusting.

15. A method for enabling dynamic memory cache size adjustment, the method comprising:

determining if a memory device supports a particular file system; and

enabling dynamic memory cache size adjustment.

16. The method of claim 15 wherein determining if the memory device supports the particular file system comprises determining if the file system of the memory device supports dynamic cache size adjustment and enabling dynamic memory cache size adjustment.

17. The method of claim 15 wherein determining if the memory device supports the particular file system comprises determining if a command is received that supports a protocol that allows deletion of a range of logical block addresses.

18. The method of claim 15 wherein dynamic memory cache size adjustment is disabled if either the particular file system does not support dynamic memory cache size adjustment or a command is not received that supports deletion of a range of logical block addresses of the memory device.

19. A method for dynamic memory cache size adjustment in a memory device, the method comprising:

enabling dynamic memory cache size adjustment responsive to the memory device supporting one of a particular file system or deletion of a range of logical block addresses of the memory device;

determining available memory space in a memory array of the memory device; and

adjusting the memory cache size in the memory array responsive to the available memory space.

20. The method of claim 19 wherein adjusting the memory cache size comprises adjusting the memory cache size linearly responsive to the available memory space.

21. The method of claim 19 wherein adjusting the memory cache size comprises adjusting the memory cache size as a step function of the available memory space.

22. The method of claim 19 wherein the memory cache size is adjusted when the available memory reaches each of a plurality of available memory thresholds.

23. A memory device comprising:

an array of memory cells comprising a memory cache; and

memory control circuitry coupled to the array of memory cells and configured to determine available memory in the array of memory cells and adjust a size of the memory cache responsive to the available memory.

24. The memory device of claim 23 wherein adjusting the size of the memory cache comprises adjusting a number of blocks of the array whose memory cells are programmed as SLC cells.

25. The memory device of claim 23 wherein the array of memory cells comprise one of a NAND or a NOR architecture.

26. The memory device of claim 23 wherein the memory control circuitry is configured to adjust the size of the memory cache dynamically as a function of whether the available memory is increasing or decreasing over a particular time period.

27. A memory system comprising:

a memory device and a controller configured to implement a file system on the memory device, wherein the memory device comprises;

an array of memory cells comprising a memory cache; and

memory control circuitry coupled to the array of memory cells and one of the controller or the memory control circuitry configured to determine if the file system supports dynamic memory cache size adjustment, the memory control circuitry further configured to enable or disable dynamic memory cache size adjustment responsive to the file system.

28. The memory system of claim 27 wherein the array of memory cells comprise non-volatile memory cells.

29. The memory system of claim 27 wherein the memory control circuitry is configured to increase the size of the memory cache responsive to available memory reaching one of a plurality of available memory thresholds.

30. The memory system of claim 29 wherein the plurality of available memory thresholds forms a step function of available memory.