APPARATUS AND METHODS FOR PROVIDING DATA INTEGRITY

• US 20120311381A1
• Filed: 05/31/2011
• Published: 12/06/2012
• Est. Priority Date: 05/31/2011
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Porterfield, Kent A.
• Granted Patent: US 9,086,983 B2
• Time in Patent Office: Days
• US Class Current: 714/6.22
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G06F 11/1092 Rebuilding, e.g. when physically replacing a failing disk
• CPC Class Codes: G06F 11/2053 where persistent mass storage functionality or persistent mass storage control functionality is redundant error detection or correction in information storage based on relative movement between record carrier and transducer G11B20/18

Abstract

The present disclosure includes apparatus (e.g., computing systems, memory systems, controllers, etc.) and methods for providing data integrity. One or more methods can include, for example: receiving a number of sectors of data to be written to a number of memory devices; appending first metadata corresponding to the number of sectors and including first integrity data to the number of sectors, the first metadata has a particular format; generating second integrity data to be provided in second metadata, the second integrity data corresponding to at least one of the number of sectors (wherein the second metadata has a second format); and generating third integrity data to be provided in the second metadata, the third integrity data including error data corresponding to the second integrity data and the at least one of the number of sectors.

Claims

1. An apparatus, comprising a controller configured to be coupled to a number of memory devices, the controller being configured to:

determine error occurrences associated with a number of memory operations associated with the number of memory devices; and

responsive to an indication of an error occurrence associated with a particular one of the number of memory operations, automatically initiate recovery of data associated with the particular one of the number of memory operations.

2. The apparatus of claim 1, wherein the controller is configured to maintain a count of error occurrences for each of a number of different error types.

3. The apparatus of claim 2, wherein the number of different error types includes:

correctable bit errors;

uncorrectable bit errors;

operational read errors; and

operational write errors.

4. The apparatus of claim 1, wherein the count of error occurrences for each of the number of different error types is maintained on a per block basis.

5. The apparatus of claim 4, wherein the controller is configured to:

determine a count of error occurrences associated with a block associated with the particular one of the number of different memory operations; and

retire the block responsive to the count of error occurrences associated with the block exceeding a threshold error count

6. The apparatus of claim 1, wherein the number of memory devices are untested with respect to bad block locations associated with the number memory devices.

7. The apparatus of claim 1, wherein the data associated with the particular one of the number of operations is automatically recovered using a RAID unit of the controller.

8. The apparatus of claim 1, wherein the controller includes an error correction component configured to detect and/or correct data read from the number of memory devices and written to the number of memory devices.

9. The apparatus of claim 1, wherein the controller includes circuitry configured to store management data corresponding to blocks of the number of memory devices, the management data including:

block age data;

error history data;

and availability data.

10. The apparatus of claim 1, wherein the number of memory devices comprises a number of NAND flash memory devices.

11. A method, comprising:

determining, with a controller configured to be coupled to a number of memory devices, error occurrences associated with a number of memory operations associated with the number of memory devices; and

responsive to an indication of an error occurrence associated with a particular one of the number of memory operations, automatically initiating recovery of data associated with the particular one of the number of memory operations.

12. The method of claim 11, including maintaining a count of error occurrences for each of a number of different error types.

13. The method of claim 12, wherein the number of different error types includes:

correctable bit errors;

uncorrectable bit errors;

operational read errors; and

operational write errors.

14. The method of claim 11, including maintaining the count of error occurrences for each of the number of different error types on a per block basis.

15. The method of claim 14, further including:

determining a count of error occurrences associated with a block associated with the particular one of the number of different memory operations; and

retiring the block responsive to the count of error occurrences associated with the block exceeding a threshold error count

16. The method of claim 11, including automatically recovering the data associated with the particular one of the number of operations using a RAID unit of the controller.

17. The method of claim 11, including determining bad blocks within the number of memory devices without performing manufacturing testing to determine bad blocks.

18. The method of claim 11, wherein the method includes storing management data corresponding to blocks of the number of memory devices, the management data including:

block age data;

error history data; and

availability data.

19. An apparatus, comprising a controller configured to be coupled to a number of memory devices, the controller being configured to:

determine error occurrences associated with a number of memory operations associated with the number of memory devices; and

responsive to an indication of an error occurrence associated with a particular one of the number of memory operations, automatically initiate recovery of data associated with the particular one of the number of memory operations while maintaining integrity of data transferred between a host interface and the number of memory devices.

20. The apparatus of claim 19, wherein the controller is configured to automatically initiate recovery of data associated with the particular number of memory operations while the controller is performing a number of read and/or write operations.