MULTIPORT MEMORY ELEMENT CIRCUITRY

• US 20120311401A1
• Filed: 05/31/2011
• Published: 12/06/2012
• Est. Priority Date: 05/31/2011
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Lee, Shih-Lin S., McElheny, Peter J., Sinha, Shankar, Singh, Preminder
• Granted Patent: US 8,755,218 B2
• Time in Patent Office: Days
• US Class Current: 714/763
• CPC Class Codes: G06F 12/1425 the protection being physical, e.g. cell, word, block
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

Integrated circuits with multiport memory elements may be provided. A multiport memory element may include a latching circuit, a first set of address transistors, and a second set of address transistors. The latching circuit may include cross-coupled inverters, each of which includes a pull-up transistor and a pull-down transistor. The first set of address transistors may couple the latching circuit to a write port, whereas the second set of address transistors may couple the latching circuit to a read port. The pull-down transistors and the second set of address transistors may have body bias terminals that are controlled by a control signal. During data loading operations, the control signal may be temporarily elevated to weaken the pull-down transistors and the second set of address transistors to improve the write margin of the multiport memory element.

Claims

1. Memory element circuitry comprising:

a storage element;

at least one write access transistor coupled to the storage element;

at least one read access transistor coupled to the storage element; and

control circuitry operable to weaken the at least one read access transistor while loading data into the storage element using the at least one write access transistor.

2. The memory element circuitry defined in claim 1, wherein the at least one read access transistor comprises a body bias terminal, and wherein the control circuitry is operable to weaken the at least one read access transistor by applying a reverse bias voltage to the body bias terminal of the at least one read access transistor while loading the data into the storage element using the at least one write access transistor.

3. The memory element circuitry defined in claim 1, wherein the at least one read access transistor comprises a first gate, wherein the at least one write access transistor comprises a second gate, wherein the control circuitry is operable to weaken the at least one read access transistor by applying a first voltage to the first gate while applying a second voltage to the second gate to load the data into the storage element using the at least one write access transistor, and wherein the first voltage is less than the second voltage.

4. The memory element circuitry defined in claim 1, wherein the storage element includes at least one storage element transistor that is weakened by the control circuitry while loading the data into the storage element using the at least one write access transistor.

5. The memory element circuitry defined in claim 4, wherein the at least one read access transistor and the storage element transistor each comprise a body bias terminal, and wherein the control circuitry is operable to weaken the at least one read access transistor and the storage element transistor by applying a reverse bias voltage to the body bias terminals of the at least one read access transistor and the storage element transistor while loading the data into the storage element using the at least one write access transistor.

6. The memory element circuitry defined in claim 4, wherein the storage element transistor comprises a body bias terminal, and wherein the control circuitry is operable to weaken the storage element transistor by applying a reverse bias voltage to the body bias terminal of the storage element transistor while loading the data into the storage element using the at least one write access transistor.

7. The memory element circuitry defined in claim 6, wherein the storage element transistor comprises an re-channel transistor.

8. The memory element circuitry defined in claim 6, wherein the storage element transistor comprises a p-channel transistor.

9. The memory element circuitry defined in claim 1 further comprising:

an additional write access transistor operable to load data into the storage element.

10. The memory element circuitry defined in claim 9 further comprising:

an additional read access transistor coupled to the storage element, wherein the control circuitry is operable to weaken the storage element, the at least one read access transistor, and the additional read access transistor by applying a reverse body bias voltage to at least a pair of transistors in the storage element, the at least one read access transistor, and the additional read access transistor while loading the data into the storage element using the at least one write access transistor and the additional write access transistor.

11. The memory element circuitry defined in claim 1 further comprising:

error correction circuitry operable to detect and correct errors in the storage element.

12. The memory element circuitry defined in claim 11, wherein the error correction circuitry comprises an error-correcting code circuit.

13. A method of loading data into a memory element, wherein the memory element comprises a storage element, at least one write access transistor, and at least one read access transistor, the method comprising:

simultaneously weakening the at least one read access transistor and the storage element when loading data into the storage element using the at least one write access transistor.

14. The method defined in claim 13, wherein simultaneously weakening the at least one read access transistor and the storage element comprises simultaneously weakening the at least one read access transistor and the storage element during a read-disturb write by adjusting at least one body bias signal associated with the memory element.

15. The method defined in claim 13, wherein the storage element comprises at least one storage element transistor, wherein the at least one read access transistor and the storage element transistor each comprise a body bias terminal, and wherein simultaneously weakening the at least one read access transistor and the storage element comprises:

applying a reverse bias voltage to the body bias terminal of the at least one read access transistor and the body bias terminal of the storage element transistor during a read-disturb write.

16. The method defined in claim 13, wherein the at least one read access transistor comprises a pair of read access transistors coupled to the storage element, wherein the at least one read access transistor comprises a first gate, and wherein the at least one write access transistor comprises a second gate, the method further comprising:

applying a first voltage to the first gate while applying a second voltage to the second gate during a read-disturb write, wherein the first voltage is less than the second voltage.

17. The method defined in claim 13, wherein the at least one read access transistor comprises an n-channel read access transistor, wherein the storage element comprises at least one n-channel transistor, and wherein simultaneously weakening the at least one read access transistor and the storage element comprises:

simultaneously weakening the n-channel read access transistor and the n-channel transistor of the storage element.

18. A memory element comprising:

a storage element having at least two transistor pairs, each of which includes a p-channel transistor and an n-channel transistor coupled in series;

at least one write address transistor; and

at least one read address transistor, wherein the n-channel transistors of the storage element have body bias terminals that are operable to receive an adjustable body bias voltage during a read-disturb write in which data is loaded into the storage element, and wherein the p-channel transistors of the storage element are operable to receive a fixed body bias voltage during the read-disturb write.

19. The memory element defined in claim 18, wherein the n-channel transistors of the storage element each comprise a body bias terminal, and wherein the body bias terminals of the n-channel transistors are operable to receive an adjustable body bias voltage to reverse bias the n-channel transistors during the read-disturb write.

20. The memory element defined in claim 18, wherein the n-channel transistors of the storage element and the at least one read address transistor each comprise a body bias terminal, and wherein the body bias terminals of the n-channel transistors and the at least one read address transistor are operable to receive the adjustable body bias voltage to reverse bias the n-channel transistors and the at least one read address transistor during the read-disturb write.