METAL OXIDE TFT WITH IMPROVED SOURCE/DRAIN CONTACTS

• US 20120313092A1
• Filed: 06/08/2011
• Published: 12/13/2012
• Est. Priority Date: 06/08/2011
• Status: Active Grant

• Current Assignee: Fantasy Shine Limited
• Original Assignee: CBRITE Inc.
• Inventors: Shieh, Chan-Long, Yu, Gang, Foong, Fatt
• Granted Patent: US 8,679,905 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 21/428 using electromagnetic radiation, e.g. laser radiation
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A method of forming ohmic source/drain contacts in a metal oxide semiconductor thin film transistor includes providing a gate, a gate dielectric, a high carrier concentration metal oxide semiconductor active layer with a band gap and spaced apart source/drain metal contacts in a thin film transistor configuration. The spaced apart source/drain metal contacts define a channel region in the active layer. An oxidizing ambient is provided adjacent the channel region and the gate and the channel region are heated in the oxidizing ambient to reduce the carrier concentration in the channel area. Alternatively or in addition each of the source/drain contacts includes a very thin layer of low work function metal positioned on the metal oxide semiconductor active layer and a barrier layer of high work function metal is positioned on the low work function metal.

Claims

1. A method of forming an active layer for a TFT with areas of different carrier densities, the method comprising the steps of:

providing a substrate with a gate, a layer of gate dielectric adjacent the gate, and a layer of high carrier concentration metal oxide semiconductor material positioned on the gate dielectric opposite the gate; and

oxidizing a channel portion of the layer of metal oxide semiconductor material aligned with the gate to reduce the carrier concentration of the channel portion, contact portions on both sides of the channel portion retaining the high carrier concentration.

2. A method of forming ohmic source/drain contacts in a metal oxide semiconductor thin film transistor comprising the steps of:

providing a gate, a gate dielectric, a high carrier concentration metal oxide semiconductor active layer with a band gap and spaced apart source/drain metal contacts in a thin film transistor configuration, the spaced apart source/drain metal contacts defining a channel region in the active layer;

providing an oxidizing ambient adjacent the channel region; and

heating the gate and the channel region in the oxidizing ambient to reduce the carrier concentration in the channel area.

3. A method as claimed in claim 2 wherein the step of heating the gate and the channel region includes using a radiation source, including one of a lamp or a pulsed laser light, with photon energy below the bandgap of the metal oxide layer.

4. A method as claimed in claim 3 wherein the step of heating includes using a pulsed laser light in conjunction with a gate dielectric and a high carrier concentration metal oxide semiconductor active layer that are transparent to the pulsed laser light, and the spaced apart source/drain metal contacts being formed after the heating step.

5. A method as claimed in claim 2 wherein the carrier concentration in the metal oxide semiconductor active layer is greater than approximately 1E18/cm3.

6. A method as claimed in claim 2 wherein the carrier concentration in the channel region of the metal oxide semiconductor active layer is reduced to less than 1E18/cm3.

7. A method as claimed in claim 4 further including the steps of forming each of the source/drain metal contacts with a first portion including a low work function metal and a high work function barrier metal, the work function of the low work function metal being one of equal to and lower than a work function of the metal oxide semiconductor active layer, and the work function of the barrier material being one of equal to and greater than the work function of the metal oxide semiconductor active layer, the first portion being positioned on the metal oxide semiconductor active layer, and a second portion of high conductivity metal positioned on the first portion.

8. A method as claimed in claim 4 further including the steps of forming each of the source/drain metal contacts with a very thin layer of low work function metal positioned on the metal oxide semiconductor active layer, the work function of the low work function metal being one of equal to and lower than a work function of the metal oxide semiconductor active layer, and a barrier layer of high work function metal positioned on the low work function metal, the work function of the high work function metal being one of equal to and greater than the work function of the metal oxide semiconductor active layer.

9. A method as claimed in claim 7 where the low work function metal has a work function lower than a work function of approximately 4 eV.

10. A method as claimed in claim 7 where the high work function barrier metal has a work function higher than a work function of approximately 4 eV.

11. A method as claimed in claim 2 where, in the step of heating the gate and the channel region, the source/drain metal contacts shield the contact portions of the high carrier concentration metal oxide semiconductor active layer on each side of the channel region from the oxidizing ambient, whereby the contact portions on both sides of the channel portion retain the high carrier concentration.

12. A method as claimed in claim 2 including in addition the step of forming a passivation layer over at least the channel region between the source/drain metal contacts, and where, in the step of heating the gate and the channel region, the passivation layer conveys oxygen therethrough during the heating step to provide the oxidizing ambient.

13. A method as claimed in claim 12 wherein the passivation layer includes material containing oxygen, the oxygen being released during the heating step to provide the oxidizing ambient.

14. A method as claimed in claim 2 in the step of providing a gate, a gate dielectric, a high carrier concentration metal oxide semiconductor active layer with a band gap and spaced apart source/drain metal contacts further including an etch stop passivation layer positioned in overlying relationship on the channel region of the metal oxide semiconductor active layer and partially beneath the source/drain metal contacts, the etch stop passivation layer being formed with insulating material that has a glass transition temperature (Tg), below the Tg the insulating material functions as a chemical barrier to O₂, H₂O, H₂, N₂, and to chemicals used in following fabrication processes above the etch stop passivation layer, and above the Tg the insulating material behaves as semi-liquid with high viscosity and with sufficient mobility to oxygen, hydrogen, and nitrogen atoms.

15. A method of forming ohmic source/drain contacts in a metal oxide semiconductor thin film transistor comprising the steps of:

providing a substrate with a gate, a layer of gate dielectric overlying the gate, and a layer of high carrier concentration metal oxide semiconductor material overlying the gate dielectric opposite the gate;

providing an oxidizing ambient adjacent the layer of metal oxide semiconductor material;

heating the gate and an adjacent channel area in the metal oxide semiconductor material in the oxidizing ambient to reduce the carrier concentration in the channel area while retaining the high carrier concentration in areas on both sides of the channel area; and

forming spaced apart source/drain metal contacts on the metal oxide semiconductor material, the spaced apart source/drain metal contacts being positioned one on each side of the channel region on the high carrier concentration areas in the metal oxide semiconductor material.

16. A method as claimed in claim 15 wherein the carrier concentration in the metal oxide semiconductor active layer is greater than approximately 1E18/cm3.

17. A method as claimed in claim 15 wherein the carrier concentration in the channel region of the metal oxide semiconductor active layer is reduced to less than 1E18/cm3.

18. A method as claimed in claim 15 wherein the step of heating the gate defines the channel region of the metal oxide

19. An active layer for a TFT with areas of different carrier densities comprising:

a substrate with a gate, a layer of gate dielectric adjacent the gate, and a layer of high carrier concentration metal oxide semiconductor material positioned on the gate dielectric opposite the gate; and

a channel portion of the layer of metal oxide semiconductor material aligned with the gate oxidized to reduce the carrier concentration of the channel portion, contact portions on both sides of the channel portion retaining the high carrier concentration.

20. An active layer for a TFT with areas of different carrier densities as claimed in claim 19 wherein the carrier concentration in the contact portions of the metal oxide semiconductor active layer is greater than approximately 1E18/cm3.

21. An active layer for a TFT with areas of different carrier densities as claimed in claim 19 wherein the carrier concentration in the channel portion of the metal oxide semiconductor active layer is reduced to less than 1E18/cm3.

22. A metal to metal oxide low resistance ohmic contact in a metal oxide semiconductor thin film transistor comprising:

a gate, a gate dielectric, a high carrier concentration metal oxide semiconductor active layer with a band gap and spaced apart source/drain metal contacts in a thin film transistor configuration, the spaced apart source/drain metal contacts defining a channel region in the active layer; and

portions of the metal oxide semiconductor active layer in contact with the source/drain metal contacts having a carrier concentration greater than a carrier concentration in the channel region.

23. A metal to metal oxide low resistance ohmic contact in a metal oxide semiconductor thin film transistor as claimed in claim 22 wherein the carrier concentration in the portions of the metal oxide semiconductor active layer in contact with the source/drain metal contacts is greater than approximately 1E18/cm3.

24. A metal to metal oxide low resistance ohmic contact in a metal oxide semiconductor thin film transistor as claimed in claim 23 wherein the carrier concentration in the channel region of the metal oxide semiconductor active layer is reduced to less than 1E18/cm3.

25. A metal to metal oxide low resistance ohmic contact in a metal oxide semiconductor thin film transistor as claimed in claim 22 wherein each of the source/drain metal contacts has a first portion including a low work function metal and a high work function barrier metal, the work function of the low work function metal being one of equal to and lower than a work function of the metal oxide semiconductor active layer, and the work function of the barrier material being one of equal to and greater than the work function of the metal oxide semiconductor active layer, the first portion being positioned on the metal oxide semiconductor active layer, and a second portion of high conductivity metal positioned on the first portion.

26. A metal to metal oxide low resistance ohmic contact in a metal oxide semiconductor thin film transistor as claimed in claim 25 wherein the low work function metal and the high work function barrier metal are mixed in a single layer.

27. A metal to metal oxide low resistance ohmic contact in a metal oxide semiconductor thin film transistor as claimed in claim 25 wherein the low work function metal and the high work function barrier metal are each formed as a separate layer.

28. A metal to metal oxide low resistance ohmic contact in a metal oxide semiconductor thin film transistor as claimed in claim 22 further including source/drain metal contacts with a very thin layer of low work function metal positioned on the metal oxide semiconductor active layer, the work function of the low work function metal being one of equal to and lower than a work function of the metal oxide semiconductor active layer, and a barrier layer of high work function metal positioned on the low work function metal, the work function of the high work function metal being one of equal to and greater than the work function of the metal oxide semiconductor active layer.

29. A metal to metal oxide low resistance ohmic contact in a metal oxide semiconductor thin film transistor as claimed in claim 28 where in the very thin layer of low work function metal the work function is lower than a work function of approximately 4 eV.

30. A metal to metal oxide low resistance ohmic contact in a metal oxide semiconductor thin film transistor as claimed in claim 28 where in the barrier layer of high work function metal the work function is higher than a work function of approximately 4 eV.

31. A metal to metal oxide low resistance ohmic contact in a metal oxide semiconductor thin film transistor as claimed in claim 22 further including an etch stop passivation layer positioned in overlying relationship on the channel region of the metal oxide semiconductor active layer, the etch stop passivation layer being formed with insulating material that has a glass transition temperature (Tg), below the Tg the insulating material functions as a chemical barrier to O₂, H₂O, H₂, N₂, and to chemicals used in following fabrication processes above the etch stop passivation layer, and above the Tg the insulating material behaves as semi-liquid with high viscosity and with sufficient mobility to oxygen, hydrogen, and nitrogen atoms.

32. A metal to metal oxide low resistance ohmic contact in a metal oxide semiconductor thin film transistor as claimed in claim 31 wherein the insulating material of the etch stop passivation layer includes one of an inorganic material including “

liquid glass”

material or silicones, including WL5150, WL-3010, or Degussa.

33. A metal to metal oxide low resistance ohmic contact in a metal oxide semiconductor thin film transistor as claimed in claim 31 wherein the insulating material of the etch stop passivation layer includes one of an organic material selected from one of the following chemical groups:

—

O—

, —

COOH, —

C═

O, —

O—

O—

, O═

C—

N—

C═

O, —

C—

OH, and —

C—

H.

34. A metal to metal oxide low resistance ohmic contact in a metal oxide semiconductor thin film transistor comprising:

a gate, a gate dielectric, a high carrier concentration metal oxide semiconductor active layer with a band gap and spaced apart source/drain metal contacts in a thin film transistor configuration;

each of the source/drain contacts including a very thin layer of low work function metal positioned on the metal oxide semiconductor active layer, the work function of the low work function metal being one of equal to and lower than a work function of the metal oxide semiconductor active layer; and

each of the source/drain contacts including a barrier layer of high work function metal positioned on the low work function metal, the work function of the high work function metal being one of equal to and greater than the work function of the metal oxide semiconductor active layer.

35. A metal to metal oxide low resistance ohmic contact in a metal oxide semiconductor thin film transistor as claimed in claim 34 where in the very thin layer of low work function metal the work function is lower than a work function of approximately 4 eV.

36. A metal to metal oxide low resistance ohmic contact in a metal oxide semiconductor thin film transistor as claimed in claim 34 where in the barrier layer of high work function metal the work function is higher than a work function of approximately 4 eV.

37. A metal to metal oxide low resistance ohmic contact in a metal oxide semiconductor thin film transistor as claimed in claim 34 wherein the spaced apart source/drain metal contacts define a channel region in the active layer, and portions of the metal oxide semiconductor active layer in contact with the source/drain metal contacts having a carrier concentration greater than a carrier concentration in the channel region.

38. A metal to metal oxide low resistance ohmic contact in a metal oxide semiconductor thin film transistor as claimed in claim 37 wherein the carrier concentration in the portions of the metal oxide semiconductor active layer in contact with the source/drain metal contacts is greater than approximately 1E18/cm3.

39. A metal to metal oxide low resistance ohmic contact in a metal oxide semiconductor thin film transistor as claimed in claim 37 wherein the carrier concentration in the channel region of the metal oxide semiconductor active layer is reduced to less than 1E18/cm3.