SELF-ALIGNED TRENCH CONTACT AND LOCAL INTERCONNECT WITH REPLACEMENT GATE PROCESS

• US 20120313148A1
• Filed: 06/10/2011
• Published: 12/13/2012
• Est. Priority Date: 06/10/2011
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Schultz, Richard T.
• Granted Patent: US 8,564,030 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

A semiconductor device fabrication process includes forming insulating mandrels over one or more replacement metal gates on a semiconductor substrate. The mandrels include a first insulating material. Each mandrel has approximately the same width as its underlying gate with each mandrel being at least as wide as its underlying gate. Mandrel spacers are formed around each insulating mandrel. The mandrel spacers include the first insulating material. Each mandrel spacer has a profile that slopes from being wider at the bottom to narrower at the top. A second insulating layer of the second insulating material is formed over the transistor. Trenches to the sources and drains of the gates are formed by removing the second insulating material from portions of the transistor between the mandrels. Trench contacts to the sources and drains of the gates are formed by depositing conductive material in the first trenches.

Claims

1. A semiconductor device fabrication process, comprising:

providing a transistor comprising one or more replacement metal gates on a semiconductor substrate, wherein the transistor comprises gate spacers of a first insulating material around each gate and a first insulating layer of a second insulating material between the gates and gate spacers, and wherein at least some of the second insulating material overlies sources and drains of the gates;

forming one or more insulating mandrels aligned over the gates, wherein the insulating mandrels comprise the first insulating material, and wherein each insulating mandrel has approximately the same width as its underlying gate with each mandrel being at least as wide as its underlying gate;

forming mandrel spacers around each insulating mandrel, wherein the mandrel spacers comprise the first insulating material, and wherein each mandrel spacer has a profile that slopes from being wider at the bottom to narrower at the top;

forming a second insulating layer of the second insulating material over the transistor;

forming one or more first trenches to the sources and drains of the gates by removing the second insulating material from portions of the transistor between the insulating mandrels, wherein at least a portion of each mandrel spacer is exposed in each of the first trenches; and

forming trench contacts to the sources and drains of the gates by depositing conductive material in the first trenches, wherein the trench contacts are wider at the top than at the bottom.

2. The process of claim 1, wherein the edges of the insulating mandrels extend past the edges of the gates.

3. The process of claim 1, wherein the edges of the mandrel spacers extend past the edges of the gate spacers.

4. The process of claim 1, further comprising forming the first trenches to the sources and drains by removing the second insulating material in a process selective to remove second insulating material but not first insulating material.

5. The process of claim 1, further comprising forming a thin layer of the second insulating material over the transistor prior to forming the insulating mandrels.

6. The process of claim 5, wherein the thin layer of the second insulating material provides an etch stop layer above the gates and gate spacers during formation of the insulating mandrels.

7. The process of claim 1, wherein the second insulating layer encapsulates the transistor in the second insulating material.

8. The process of claim 1, wherein the trench contacts comprise a slope determined by the slope of the mandrel spacers.

9. The process of claim 1, wherein the trench contacts are inhibited from shorting to the gates.

10. The process of claim 1, wherein forming the insulating mandrels is accomplished using a designed resist pattern that is also used to form the gates.

11. The process of claim 1, wherein forming the insulating mandrels is accomplished using a CAD (computer-aided design) designed resist pattern that defines the insulating mandrels.

12. The process of claim 1, further comprising:

forming a third insulating layer over the transistor;

forming one or more second trenches through the third insulating layer to the trench contacts by removing portions of the third insulating layer; and

forming local interconnects to the trench contacts by depositing conductive material in the trenches formed through the third insulating layer.

13. The process of claim 1, further comprising forming a contact to at least one gate by removing portions of the first insulating material above the gate to form a trench to the gate and depositing conductive material into the trench to form the contact to the gate.

14. The process of claim 13, further comprising removing portions of the first insulating material above the gate in a process selective to remove first insulating material but not second insulating material such that the trench is aligned to the gate.

15. A semiconductor device, comprising:

one or more replacement metal gates on a semiconductor substrate;

gate spacers of a first insulating material around each gate;

a first insulating layer of a second insulating material between the gates and gate spacers, wherein at least some of the second insulating material overlies sources and drains of the gates;

one or more insulating mandrels aligned over the gates, wherein the insulating mandrels comprise the first insulating material, and wherein each insulating mandrel has approximately the same width as its underlying gate with each mandrel being at least as wide as its underlying gate;

mandrel spacers around each insulating mandrel, wherein the mandrel spacers comprise the first insulating material, and wherein each mandrel spacer has a profile that slopes from being wider at the bottom to narrower at the top;

one or more trench contacts to the sources and drains of the gates between the mandrel spacers, wherein the trench contacts have a profile that matches the slope of the mandrel spacers such that the trench contacts are wider at the top than at the bottom;

a third insulating layer over the transistor; and

one or more local interconnects that contact the trench contacts through the third insulating layer.

16. The device of claim 15, wherein the edges of the insulating mandrels extend past the edges of the gates.

17. The device of claim 15, wherein the edges of the mandrel spacers extend past the edges of the gate spacers.

18. The device of claim 15, further comprising a thin layer of the second insulating material between the insulating mandrels and the gates.

19. The device of claim 15, wherein the trench contacts comprise a slope determined by the slope of the mandrel spacers.

20. The device of claim 15, wherein the trench contacts are not shorted to the gates.

21. The device of claim 15, further comprising an interconnect to at least one gate through the third insulating layer and the insulating mandrel above the gate.

22. A computer readable storage medium storing a plurality of instructions which, when executed, generate one or more resist patterns useable in a semiconductor process that comprises:

providing a transistor comprising one or more replacement metal gates on a semiconductor substrate, wherein the transistor comprises gate spacers of a first insulating material around each gate and a first insulating layer of a second insulating material between the gates and gate spacers, and wherein at least some of the second insulating material overlies sources and drains of the gates;

forming one or more insulating mandrels aligned over the gates, wherein the insulating mandrels comprise the first insulating material, and wherein each insulating mandrel has approximately the same width as its underlying gate with each mandrel being at least as wide as its underlying gate;

forming mandrel spacers around each insulating mandrel, wherein the mandrel spacers comprise the first insulating material, and wherein each mandrel spacer has a profile that slopes from being wider at the bottom to narrower at the top;

forming a second insulating layer of the second insulating material over the transistor;

forming one or more first trenches to the sources and drains of the gates by removing the second insulating material from portions of the transistor between the insulating mandrels, wherein at least a portion of each mandrel spacer is exposed in each of the first trenches; and

forming trench contacts to the sources and drains of the gates by depositing conductive material in the first trenches, wherein the trench contacts are wider at the top than at the bottom.

23. A computer readable storage medium storing a plurality of instructions which, when executed, generate a semiconductor device that comprises:

one or more replacement metal gates on a semiconductor substrate;

gate spacers of a first insulating material around each gate;

a first insulating layer of a second insulating material between the gates and gate spacers, wherein at least some of the second insulating material overlies sources and drains of the gates;

one or more insulating mandrels aligned over the gates, wherein the insulating mandrels comprise the first insulating material, and wherein each insulating mandrel has approximately the same width as its underlying gate with each mandrel being at least as wide as its underlying gate;

mandrel spacers around each insulating mandrel, wherein the mandrel spacers comprise the first insulating material, and wherein each mandrel spacer has a profile that slopes from being wider at the bottom to narrower at the top;

one or more trench contacts to the sources and drains of the gates between the mandrel spacers, wherein the trench contacts have a profile that matches the slope of the mandrel spacers such that the trench contacts are wider at the top than at the bottom;

a third insulating layer over the transistor; and

one or more local interconnects that contact the trench contacts through the third insulating layer.