SELF-ALIGNED TRENCH CONTACT AND LOCAL INTERCONNECT WITH REPLACEMENT GATE PROCESS
First Claim
1. A semiconductor device fabrication process, comprising:
- providing a transistor comprising one or more replacement metal gates on a semiconductor substrate, wherein the transistor comprises gate spacers of a first insulating material around each gate and a first insulating layer of a second insulating material between the gates and gate spacers, and wherein at least some of the second insulating material overlies sources and drains of the gates;
forming one or more insulating mandrels aligned over the gates, wherein the insulating mandrels comprise the first insulating material, and wherein each insulating mandrel has approximately the same width as its underlying gate with each mandrel being at least as wide as its underlying gate;
forming mandrel spacers around each insulating mandrel, wherein the mandrel spacers comprise the first insulating material, and wherein each mandrel spacer has a profile that slopes from being wider at the bottom to narrower at the top;
forming a second insulating layer of the second insulating material over the transistor;
forming one or more first trenches to the sources and drains of the gates by removing the second insulating material from portions of the transistor between the insulating mandrels, wherein at least a portion of each mandrel spacer is exposed in each of the first trenches; and
forming trench contacts to the sources and drains of the gates by depositing conductive material in the first trenches, wherein the trench contacts are wider at the top than at the bottom.
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Accused Products
Abstract
A semiconductor device fabrication process includes forming insulating mandrels over one or more replacement metal gates on a semiconductor substrate. The mandrels include a first insulating material. Each mandrel has approximately the same width as its underlying gate with each mandrel being at least as wide as its underlying gate. Mandrel spacers are formed around each insulating mandrel. The mandrel spacers include the first insulating material. Each mandrel spacer has a profile that slopes from being wider at the bottom to narrower at the top. A second insulating layer of the second insulating material is formed over the transistor. Trenches to the sources and drains of the gates are formed by removing the second insulating material from portions of the transistor between the mandrels. Trench contacts to the sources and drains of the gates are formed by depositing conductive material in the first trenches.
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Citations
23 Claims
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1. A semiconductor device fabrication process, comprising:
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providing a transistor comprising one or more replacement metal gates on a semiconductor substrate, wherein the transistor comprises gate spacers of a first insulating material around each gate and a first insulating layer of a second insulating material between the gates and gate spacers, and wherein at least some of the second insulating material overlies sources and drains of the gates; forming one or more insulating mandrels aligned over the gates, wherein the insulating mandrels comprise the first insulating material, and wherein each insulating mandrel has approximately the same width as its underlying gate with each mandrel being at least as wide as its underlying gate; forming mandrel spacers around each insulating mandrel, wherein the mandrel spacers comprise the first insulating material, and wherein each mandrel spacer has a profile that slopes from being wider at the bottom to narrower at the top; forming a second insulating layer of the second insulating material over the transistor; forming one or more first trenches to the sources and drains of the gates by removing the second insulating material from portions of the transistor between the insulating mandrels, wherein at least a portion of each mandrel spacer is exposed in each of the first trenches; and forming trench contacts to the sources and drains of the gates by depositing conductive material in the first trenches, wherein the trench contacts are wider at the top than at the bottom. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A semiconductor device, comprising:
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one or more replacement metal gates on a semiconductor substrate; gate spacers of a first insulating material around each gate; a first insulating layer of a second insulating material between the gates and gate spacers, wherein at least some of the second insulating material overlies sources and drains of the gates; one or more insulating mandrels aligned over the gates, wherein the insulating mandrels comprise the first insulating material, and wherein each insulating mandrel has approximately the same width as its underlying gate with each mandrel being at least as wide as its underlying gate; mandrel spacers around each insulating mandrel, wherein the mandrel spacers comprise the first insulating material, and wherein each mandrel spacer has a profile that slopes from being wider at the bottom to narrower at the top; one or more trench contacts to the sources and drains of the gates between the mandrel spacers, wherein the trench contacts have a profile that matches the slope of the mandrel spacers such that the trench contacts are wider at the top than at the bottom; a third insulating layer over the transistor; and one or more local interconnects that contact the trench contacts through the third insulating layer. - View Dependent Claims (16, 17, 18, 19, 20, 21)
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22. A computer readable storage medium storing a plurality of instructions which, when executed, generate one or more resist patterns useable in a semiconductor process that comprises:
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providing a transistor comprising one or more replacement metal gates on a semiconductor substrate, wherein the transistor comprises gate spacers of a first insulating material around each gate and a first insulating layer of a second insulating material between the gates and gate spacers, and wherein at least some of the second insulating material overlies sources and drains of the gates; forming one or more insulating mandrels aligned over the gates, wherein the insulating mandrels comprise the first insulating material, and wherein each insulating mandrel has approximately the same width as its underlying gate with each mandrel being at least as wide as its underlying gate; forming mandrel spacers around each insulating mandrel, wherein the mandrel spacers comprise the first insulating material, and wherein each mandrel spacer has a profile that slopes from being wider at the bottom to narrower at the top; forming a second insulating layer of the second insulating material over the transistor; forming one or more first trenches to the sources and drains of the gates by removing the second insulating material from portions of the transistor between the insulating mandrels, wherein at least a portion of each mandrel spacer is exposed in each of the first trenches; and forming trench contacts to the sources and drains of the gates by depositing conductive material in the first trenches, wherein the trench contacts are wider at the top than at the bottom.
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23. A computer readable storage medium storing a plurality of instructions which, when executed, generate a semiconductor device that comprises:
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one or more replacement metal gates on a semiconductor substrate; gate spacers of a first insulating material around each gate; a first insulating layer of a second insulating material between the gates and gate spacers, wherein at least some of the second insulating material overlies sources and drains of the gates; one or more insulating mandrels aligned over the gates, wherein the insulating mandrels comprise the first insulating material, and wherein each insulating mandrel has approximately the same width as its underlying gate with each mandrel being at least as wide as its underlying gate; mandrel spacers around each insulating mandrel, wherein the mandrel spacers comprise the first insulating material, and wherein each mandrel spacer has a profile that slopes from being wider at the bottom to narrower at the top; one or more trench contacts to the sources and drains of the gates between the mandrel spacers, wherein the trench contacts have a profile that matches the slope of the mandrel spacers such that the trench contacts are wider at the top than at the bottom; a third insulating layer over the transistor; and one or more local interconnects that contact the trench contacts through the third insulating layer.
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Specification