MODULAR DIE AND MASK FOR SEMICONDUCTOR PROCESSING

• US 20120313179A1
• Filed: 06/11/2012
• Published: 12/13/2012
• Est. Priority Date: 08/04/2009
• Status: Abandoned Application

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Croft, Scott
• Application Number:
  US13/493,770
• Publication Number:
  US 20120313179A1
• Time in Patent Office: Days
• US Class Current: 257/368
• CPC Class Codes: G03F 1/00 Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
• CPC Class Codes: H01L 21/32139 using masks

Abstract

Modular dies and modular masks for the manufacture of semiconductor devices are described. The modular mask can be used repeatedly to make multiple, substantially-similar modular dies. The modular die contains a substrate with an integrated circuit and a conductive layer containing a source metal and a gate metal connected respectively to the source and gate of the integrated circuit. The gate metal is located in an outer portion of the modular die. The modular die can be made by providing the integrated circuit in first and second portions of the substrate, providing the conductive layer on both first and second portions, making a first modular die by patterning the conductive layer on the first portion using the modular mask, moving the mask to the second portion and using it to make a second modular die by patterning the conductive layer on the second portion. Other embodiments are described.

Claims

1. (canceled)

2. (canceled)

3. (canceled)

4. (canceled)

5. (canceled)

6. (canceled)

7. (canceled)

8. (canceled)

9. (canceled)

10. (canceled)

11. (canceled)

12. (canceled)

13. (canceled)

14. (canceled)

15. (canceled)

16. (canceled)

17. (canceled)

18. (canceled)

19. (canceled)

20. (canceled)

21. (canceled)

22. (canceled)

23. (canceled)

24. (canceled)

25. (canceled)

26. (canceled)

27. A modular die, comprising:

a substrate containing an integrated circuit having a source and a gate; and

a conductive layer located on the substrate, the conductive layer containing both a source metal and a gate metal that are located only in an outer portion of the modular die, the source metal being connected to the source and the gate metal being connected to the gate;

wherein the gate metal covers about 1 to about 99% of the die.

28. The modular die of claim 27, further comprising a source contact on the source metal and a gate contact on the gate metal.

29. The modular die of claim 28, further comprising a source pad on the source contact and a gate pad on the gate contact.

30. The modular die of claim 27, further comprising an active area under the gate pad.

31. The modular die of claim 30, wherein the active area under the gate pad ranges from about 1 to about 99% of the area of the die.

32. The modular die of claim 27, wherein the modular die can be used alone to form a first die layout.

33. The modular die of claim 32, wherein the modular die can be used with a substantially similar second modular die to form a second die layout.

34. The modular die of claim 33, wherein a substantially similar third modular die can be used with the first and second modular dies to form a third die layout.

35. A semiconductor device, comprising:

a modular die a substrate containing;

an integrated circuit having a source and a gate; and

a conductive layer located on a front side of the substrate, the conductive layer containing both a source metal and a gate metal that is located only in an outer portion of the modular die, the source metal being connected to the source and the gate metal being connected to the gate, wherein the gate metal covers about 1 to about 99% of the die; and

a drain on the backside of the substrate; and

a molding material encapsulating the modular die.

36. The semiconductor device of claim 35, further comprising a source contact on the source metal and a gate contact on the gate metal.

37. The semiconductor device of claim 36, further comprising a source pad on the source contact and a gate pad on the gate contact.

38. The semiconductor device of claim 35, further comprising an active area under the gate pad.

39. The semiconductor device of claim 38, wherein the active area under the gate pad ranges from about 1 to about 99% of the area of the die.

40. The semiconductor device of claim 35, wherein the modular die can be used alone to form a first die layout.

41. The semiconductor device of claim 40, wherein the modular die can be used with a substantially similar second modular die to form a second die layout.

42. The semiconductor device of claim 41, wherein a substantially similar third modular die can be used with the first and second modular dies to form a third die layout.

43. A modular mask configured to manufacture multiple, substantially similar modular dies, wherein the mask is configured to pattern a conductive layer to contain both a source metal and a gate metal that is located only in an outer portion of a first modular die, wherein the gate metal covers about 1 to about 99% of the first modular die.

44. The modular mask of claim 43, wherein the mask is configured to form the first modular die from a first wafer and a substantially similar, second modular die from the first wafer.

45. The modular mask of claim 44, wherein the mask is configured to form a substantially similar, third modular die from the first wafer.

46. The modular mask of claim 43, wherein the mask is configured to be re-used regardless of the final semiconductor device manufactured using the mask.