POLYSILICON GATE WITH NITROGEN DOPED HIGH-K DIELECTRIC AND SILICON DIOXIDE

• US 20120313186A1
• Filed: 06/08/2011
• Published: 12/13/2012
• Est. Priority Date: 06/08/2011
• Status: Abandoned Application

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: HUANG, Ching-Chien, CHIOU, Ying-Han, WANG, Ling-Sung
• Application Number:
  US13/156,006
• Publication Number:
  US 20120313186A1
• Time in Patent Office: Days
• US Class Current: 257/411
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material

Abstract

A polysilicon gate structure includes a substrate, a silicon dioxide layer disposed over the substrate, a nitrogen-doped high-k dielectric layer disposed over the silicon dioxide layer, and a polysilicon gate disposed over the nitrogen-doped high-k dielectric layer.

Claims

1. A polysilicon gate structure, comprising:

a substrate;

a silicon dioxide layer disposed over the substrate;

a nitrogen-doped high-k dielectric layer disposed over the silicon dioxide layer; and

a polysilicon gate disposed over the nitrogen-doped high-k dielectric layer.

2. The polysilicon gate structure of claim 1, wherein the substrate comprises silicon.

3. The polysilicon gate structure of claim 1, wherein the nitrogen-doped high-k dielectric layer comprises HfON.

4. The polysilicon gate structure of claim 1, wherein the polysilicon gate includes a p-type semiconductor material.

5. The polysilicon gate structure of claim 4, wherein the p-type semiconductor material is boron.

6. The polysilicon gate structure of claim 1, wherein the polysilicon gate includes an n-type semiconductor material.

7. The polysilicon gate structure of claim 1, wherein the nitrogen-doped high-k dielectric layer is doped with a nitrogen dosage from about 8% to about 9%.

8. The polysilicon gate structure of claim 1, wherein a thickness ratio of the nitrogen-doped high-k dielectric layer and the silicon dioxide layer is about 1:

4.

9. The polysilicon gate structure of claim 1, wherein a thickness of the nitrogen-doped high-k dielectric layer is about 4 Å

to about 12 Å

.

10. The polysilicon gate structure of claim 1, wherein a thickness of the silicon dioxide layer is about 15 Å

to about 45 Å

.

11. A method of fabricating a polysilicon gate structure, comprising:

forming a silicon dioxide layer over a substrate;

forming a nitrogen-doped high-k dielectric layer over the silicon dioxide layer; and

forming a polysilicon gate over the nitrogen-doped high-k dielectric layer.

12. The method of claim 11, wherein forming the nitrogen-doped high-k dielectric layer comprises:

depositing a high-k dielectric layer over the silicon dioxide layer; and

doping the high-k dielectric layer with nitrogen.

13. The method of claim 12, wherein the high-k dielectric layer with nitrogen is doped with a nitrogen dosage from about 8% to about 9%.

14. The method of claim 11, wherein forming the polysilicon gate comprises:

depositing a polysilicon layer over the nitrogen-doped high-k dielectric layer; and

doping the polysilicon layer with a semiconductor dopant.

15. The method of claim of claim 14, wherein the semiconductor dopant is a p-type semiconductor material.

16. The method of claim of claim 15, wherein the semiconductor dopant is boron.

17. The method of claim of claim 14, wherein the semiconductor dopant is an n-type semiconductor material.

18. The method of claim 11, wherein a thickness ratio of the nitrogen-doped high-k dielectric layer and the silicon dioxide layer is about 1:

4.

19. An integrated circuit having a polysilicon gate structure, comprising:

a silicon substrate;

a silicon dioxide layer disposed over the silicon substrate;

a nitrogen-doped high-k dielectric layer disposed over the silicon dioxide layer; and

a polysilicon gate including boron disposed over the nitrogen-doped high-k dielectric layer.

20. The integrated circuit of claim 19, wherein the nitrogen-doped high-k dielectric layer comprises HfON.