SEMICONDUCTOR DEVICE STRUCTURES AND THE SEPARATING METHODS THEREOF

• US 20120313249A1
• Filed: 06/07/2012
• Published: 12/13/2012
• Est. Priority Date: 06/09/2011
• Status: Active Grant

• Current Assignee: Epistar Corporation (Ennostar, Inc.)
• Original Assignee: Epistar Corporation (Ennostar, Inc.)
• Inventors: Hsu, Chia-Liang, CHEN, Shih-I, Lin, Ching-Pei, Hsu, Tzu-Chieh
• Granted Patent: US 8,765,504 B2
• Time in Patent Office: Days
• US Class Current: 257/770
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 33/0095 Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination

Abstract

A method of separating semiconductor device structures comprises steps of providing a substrate having a first surface and a second surface opposite to the first surface; forming a plurality of semiconductor epitaxial stacks on the first surface; forming a patterned resist layer covering the semiconductor epitaxial stacks and exposing part of the first surface, or covering the second surface corresponding to the semiconductor epitaxial stacks; performing a physical etching process to directly server the substrate apart from an area of the first surface or the second surface not covered by the patterned resist layer; and separating the semiconductor epitaxial stacks to form a plurality of semiconductor device structures.

Claims

1. A method of separating semiconductor device structures, comprising:

providing a substrate, comprising a first surface and a second surface opposite to the first surface;

forming a plurality of semiconductor epitaxial stacks on the first surface;

forming a patterned resist layer covering the semiconductor epitaxial stacks and exposing part of the first surface, or covering the second surface corresponding to the semiconductor epitaxial stacks;

performing a physical etching process to directly sever the substrate apart from an area of the first surface or the second surface not covered by the patterned resist layer; and

separating the semiconductor epitaxial stacks to form a plurality of semiconductor device structures.

2. The method of separating a semiconductor device structure as claimed in claim 1, further comprising the step of removing the patterned resist layer after etching the substrate by the physical etching process.

3. The method of separating a semiconductor device structure as claimed in claim 1, further comprising the step of forming a protective layer covering the semiconductor epitaxial stacks.

4. The method of separating a semiconductor device structure as claimed in claim 1, wherein the ratio of the etching rate of the etchant etching the substrate over the etching rate of the etchant etching the patterned resist layer is larger than 10.

5. The method of separating a semiconductor device structure as claimed in claim 1, wherein the physical etching process is a microblasting process.

6. The method of separating a semiconductor device structure as claimed in claim 1, wherein some of the sidewalls of the substrates of the semiconductor device structures are curved.

7. The method of separating a semiconductor device structure as claimed in claim 1, wherein the substrates of the semiconductor device structures are triangles, irregular quadrangles, and/or polygons with more than five sides.

8. The method of separating a semiconductor device structure as claimed in claim 1, further comprising forming a supporting layer on the second surface.

9. A semiconductor device structure, comprising:

a substrate comprising a first surface and a plurality of sidewalls adjacent to the first surface, wherein all of the sidewalls are roughened by microblasting; and

a semiconductor epitaxial stack formed on the first surface, comprising;

a first semiconductor material layer with a first electrical conductivity;

a second semiconductor material layer with a second electrical conductivity; and

an active layer positioned between the first semiconductor material layer and the second semiconductor material layer.

10. The semiconductor device structure as claimed in claim 9, further comprising a connecting layer positioned between the substrate and the semiconductor epitaxial stack.

11. The semiconductor device structure as claimed in claim 9, wherein the roughened surfaces has a roughness ranging from 1 micrometer and 40 micrometers.

12. The semiconductor device structure as claimed in claim 10, wherein the connecting layer is an oxide material layer, a metal layer, or an organic material layer.

13. The semiconductor device structure as claimed in claim 12, wherein the connecting layer is made of the oxide material selected from Al₂O₃, SiO₂, TiO₂, Ta₂O₅, ITO, IZO, ZnO₂, or the combination thereof.

14. The semiconductor device structure as claimed in claim 12, wherein the connecting layer is made of the metal material selected from Au, In, Sn, Cu, Ag, Ti, Al, or the combination thereof.

15. The semiconductor device structure as claimed in claim 12, wherein the connecting layer is made of the organic material selected from BCB, SOG, SINR, or the combination thereof.

16. A package type semiconductor device structure, comprising:

a substrate comprising a first surface, a second surface opposite to the first surface, and a plurality of the first sidewalls adjacent to the first surface;

a semiconductor epitaxial stack formed on the first surface, comprising;

a first semiconductor material layer with a first electrical conductivity;

a second semiconductor material layer with a second electrical conductivity;

an active layer positioned between the first semiconductor material layer and the second semiconductor material layer; and

a third surface facing the first surface and a plurality of the second sidewalls adjacent to the third surface; and

a protecting layer, covering the second surface, the first sidewalls, and the second sidewalls.

17. The package type semiconductor device structure as claimed in claim 16, further comprising a connecting layer positioned between the substrate and the semiconductor epitaxial stack.

18. The package type semiconductor device structure as claimed in claim 16, wherein the protecting layer comprises silicone.

19. The package type semiconductor device structure as claimed in claim 16, wherein the protecting layer covers all of the second surface, the first sidewalls, and the second sidewalls.