FAN-OUT WLP WITH PACKAGE

• US 20120313253A1
• Filed: 06/08/2011
• Published: 12/13/2012
• Est. Priority Date: 06/08/2011
• Status: Active Grant

• Current Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.), Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera Technologies, Inc. (Adeia Inc.)
• Inventors: Nakadaira, Yoshikuni, Masuda, Norihito, Haba, Belgacem, Mohammed, Ilyas, Damberg, Philip, Sato, Hiroaki, Hashimoto, Kiyoaki
• Granted Patent: US 8,890,304 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02379 Fan-out arrangement
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/215 Material
• CPC Class Codes: H01L 2224/24011 Deposited, e.g. MCM-D type
• CPC Class Codes: H01L 2224/24225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/245 Material
• CPC Class Codes: H01L 2224/29008 Layer connector integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73217 Layer and HDI connectors
• CPC Class Codes: H01L 2224/76155 Jetting means, e.g. ink jet
• CPC Class Codes: H01L 2224/82101 by additive methods, e.g. direct writing
• CPC Class Codes: H01L 2224/82102 using jetting, e.g. ink jet
• CPC Class Codes: H01L 2224/82103 using laser direct writing
• CPC Class Codes: H01L 2224/82104 using screen printing
• CPC Class Codes: H01L 2224/8284 Sintering
• CPC Class Codes: H01L 2224/83053 : Bonding environment
• CPC Class Codes: H01L 2224/8309 : Vacuum
• CPC Class Codes: H01L 2224/83091 : Under pressure
• CPC Class Codes: H01L 2224/8384 : Sintering
• CPC Class Codes: H01L 2224/83851 : being an anisotropic conductive adhesive
• CPC Class Codes: H01L 2224/83862 : Heat curing
• CPC Class Codes: H01L 23/13 : characterised by the shape
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/06 : Polymers
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15151 : the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A microelectronic package includes a microelectronic unit and a substrate. The microelectronic unit includes a microelectronic element having contacts on a front face. A dielectric material has a first surface substantially flush with the front face of the microelectronic element. Conductive traces have at least portions extending along the front face away from the contacts, at least some of which also extend along the first surface of the dielectric material. Contacts are connected with the traces, at least some of which are disposed at the first surface of the dielectric material. The substrate has first and second opposed surfaces and an edge extending therebetween, the first surface facing the front face of the microelectronic unit, and the second surface having a plurality of terminals thereon configured for electrical connection with at least one external component. Masses of conductive matrix material join the terminals with the redistribution contacts.

Claims

1. A microelectronic package, comprising:

a microelectronic unit, including;

a microelectronic element having a front face, edges bounding the front face, and contacts on the front face;

a dielectric material having a first surface substantially flush with the front face of the microelectronic element and extending away from the edges thereof;

conductive traces having at least portions extending along the front face away from the contacts, at least some of which also extend along the first surface of the dielectric material; and

conductive redistribution contacts connected with the traces, at least some of which are disposed at the first surface of the dielectric material; and

a substrate having first and second opposed surfaces and an edge extending therebetween, the first surface facing the front face of the microelectronic unit, and the second surface having a plurality of terminals thereon configured for electrical connection with at least one external component; and

conductive interconnects including masses of conductive matrix material joined to the redistribution contacts and electrically connected with the terminals.

2. The package of claim 1, wherein the microelectronic element is a first microelectronic element, the microelectronic unit further including a second microelectronic element having a front face, edges bounding the front face, and contacts on the first face, wherein the conductive traces extend from contacts on each of the first and second microelectronic elements.

3. The package of claim 2, wherein the substrate further includes a plurality of conductive elements that are at least part of an electrical connection between the contacts of the first microelectronic element and the contacts of the second microelectronic element.

4. The package of claim 3, wherein the terminals of the substrate are first terminals electrically interconnected with the contacts of the first microelectronic element, the substrate further including second terminals electrically interconnected with the contacts of the second microelectronic element, and wherein the conductive elements of the substrate are conductive traces that extend along the second surface of the substrate between at least some of the first terminals and respective ones of at least some of the second terminals.

5. The package of claim 1, wherein the edge of the substrate is a peripheral edge.

6. The package of claim 1, wherein the substrate includes an aperture extending between the first and second surfaces, wherein the edge is defined by the aperture, and wherein the conductive interconnects extend through the aperture along portions of the edge.

7. The package of claim 6, wherein the conductive interconnects have first ends bonded to respective ones of the redistribution contacts and second ends bonded to conductive elements formed along the second surface of the substrate, the conductive elements being connected with the terminals.

8. The package of claim 6, wherein the edge forms an angle with the second surface of the substrate, the angle being between about 25 degrees and 50 degrees.

9. The package of claim 1, wherein the conductive interconnects extend in a direction between the first and second surfaces of the substrate.

10. The package of claim 1, wherein the terminals include a solid metal post portion that extends at least partially through the substrate to an end surface located between the first and second surfaces of the substrate, and wherein the conductive interconnects are joined with the end surfaces.

11. The package of claim 1, wherein the substrate includes an element having a coefficient of thermal expansion of less than 8 parts per million per degree Celsius (“

ppm/°

C.”

).

12. The package of claim 1, wherein the substrate includes a compliant dielectric layer.

13. The package of claim 1, further including an underfill layer between a common surface including the front surface of the microelectronic element and the first surface of the dielectric layer and the first surface of the substrate.

14. A microelectronic assembly, including:

a microelectronic package of claim 1;

a circuit panel having a plurality of circuit contacts thereon; and

conductive masses joining the terminals of the substrate with respective ones of the circuit contacts.

15. A system comprising:

a microelectronic package according to claim 1 and one or more other electronic components electrically connected to the microelectronic assembly.

16. A system as claimed in claim 15 further comprising a housing, the microelectronic package and the one or more other electronic components being mounted to the housing.

17. A method for making a microelectronic package, comprising:

assembling a microelectronic unit with a substrate having first and second opposed surfaces and an edge extending therebetween, the substrate having a plurality of terminals thereon configured for electrical connection with at least one external component, the microelectronic unit including a microelectronic element having a front face with contacts thereon and edges bounding the front face, a dielectric region having a first surface substantially flush with the front face and extending away from the edges, conductive traces having portions extending along the front face away from the contacts, at least some of which further extend along the first surface of the dielectric region, and conductive redistribution contacts connected with the traces, at least some of which are disposed on the first surface of the dielectric region; and

electrically connecting the redistribution contacts and the terminals with a conductive matrix material extending within at least one opening extending through the substrate.

18. The method of claim 17, wherein the at least one opening includes a plurality of openings and the step of electrically connecting includes forming the plurality of openings after assembling the microelectronic unit with the substrate and then depositing the conductive matrix material within the plurality of openings.

19. A method for making a microelectronic package, comprising:

mounting a microelectronic unit on a substrate having first and second opposed surfaces and having a plurality of terminals configured for electrical connection with at least one external component, the substrate further having conductive interconnects extending between the first and second surfaces thereof and connected with the terminals, the microelectronic unit including a microelectronic element having a front face with contacts thereon and edges bounding the front face, a dielectric region having a first surface substantially flush with the front face and extending away from the edges, conductive traces having portions extending along the front face away from the contacts, at least some of which further extend along the first surface of the dielectric region, and conductive redistribution contacts connected with the traces, at least some of which are disposed on the first surface of the dielectric region, wherein the mounting of the microelectronic unit on the substrate is carried out such that an electrical connection is completed between the redistribution contacts and the terminals.

20. The method of claim 19, wherein the substrate further includes a plurality of apertures extending through the substrate and the conductive interconnects extend within respective ones of the apertures.

21. The method of claim 19, wherein the conductive interconnects include rigid metal structures, and the step of mounting the microelectronic unit includes joining the conductive interconnects with the redistribution contacts using a conductive bonding material.

22. The method of claim 19, further including forming an underfill layer between the front surface of the microelectronic unit and the first surface of the substrate.

23. The method of claim 19, wherein the conductive interconnects are made from a conductive bonding material, and wherein the step of mounting the microelectronic unit on the substrate includes joining the conductive interconnects with the redistribution contacts.

24. The method of claim 23, wherein the conductive bonding material is a conductive matrix material and wherein the joining of the conductive interconnects with the redistribution contacts includes heating the conductive matrix material.