SEMICONDUCTOR MEMORY DEVICE

• US 20120314482A1
• Filed: 05/23/2012
• Published: 12/13/2012
• Est. Priority Date: 06/10/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Takemura, Yasuhiko
• Granted Patent: US 8,891,285 B2
• Time in Patent Office: Days
• US Class Current: 365/149
• CPC Class Codes: G11C 11/403 with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4085 Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits

Abstract

An object is to increase the retention characteristics of a memory device formed using a semiconductor with a wide bandgap, such as an oxide semiconductor. A transistor including a back gate (a back gate transistor) is inserted in series at one end of a bit line so that the back gate is constantly at a sufficiently negative potential. The minimum potential of the bit line is set higher than that of a word line. When power is turned off, the bit line is cut off by the back gate transistor, ensuring prevention of outflow of charge accumulated in the bit line. At this time, the potential of a source or a drain (bit line) of a cell transistor is sufficiently higher than that of a gate of the cell transistor (0 V), so that the cell transistor is put in a sufficiently off state; thus, data can be retained.

Claims

1. A semiconductor memory device comprising:

a column driver;

a bit line;

a word line;

a memory cell comprising a first transistor and a capacitor; and

a second transistor including a back gate,

wherein a source of the first transistor is electrically connected to the bit line,

wherein a drain of the first transistor is electrically connected to one electrode of the capacitor,

wherein a gate of the first transistor is electrically connected to the word line,

wherein a drain of the second transistor is electrically connected to the bit line,

wherein a source of the second transistor is electrically connected to the column driver, and

wherein a potential of the back gate of the second transistor is lower than a minimum potential of the word line.

2. The semiconductor memory device according to claim 1, further comprising a third transistor including a back gate,

wherein the third transistor is provided between the column driver and the second transistor.

3. The semiconductor memory device according to claim 1, further comprising a wiring electrically connected to the back gate of the second transistor,

wherein the wiring is in a floating state.

4. The semiconductor memory device according to claim 1,

wherein the memory cell further comprises a third transistor, and

wherein the drain of the first transistor is electrically connected to a gate of the third transistor.

5. The semiconductor memory device according to claim 1, wherein a minimum potential of the bit line is higher than the minimum potential of the word line by 1 V or more.

6. The semiconductor memory device according to claim 1, further comprising one or more sense amplifiers inserted in the bit line.

7. The semiconductor memory device according to claim 1, further comprising a circuit configured to control a gate of the second transistor.

8. The semiconductor memory device according to claim 1, wherein a maximum potential of the gate of the second transistor is higher than a maximum potential of the word line by 1 V or more.

9. The semiconductor memory device according to claim 1, wherein the potential of the back gate of the second transistor is lower than a potential of any other portion.

10. The semiconductor memory device according to claim 1, wherein each of the first transistor and the second transistor comprises a semiconductor with an irreversible conductivity type.

11. The semiconductor memory device according to claim 1, wherein each of the first transistor and the second transistor comprises an oxide semiconductor.

12. The semiconductor memory device according to claim 1, wherein each of the first transistor and the second transistor comprises a semiconductor with a bandgap of 2.5 electron volts or more.

13. The semiconductor memory device according to claim 1, wherein the back gate of the second transistor is electrically connected to a negative electrode of a battery.

14. A semiconductor memory device comprising:

a column driver;

a bit line;

a word line;

a memory cell comprising a first transistor and a capacitor; and

a second transistor including a back gate,

wherein a source of the first transistor is electrically connected to the bit line,

wherein a drain of the first transistor is electrically connected to one electrode of the capacitor,

wherein a gate of the first transistor is electrically connected to the word line,

wherein the bit line is electrically connected to the column driver,

wherein the second transistor is inserted in series in the bit line, and

wherein a potential of the back gate of the second transistor is lower than a minimum potential of the word line.

15. The semiconductor memory device according to claim 14, further comprising a third transistor including a back gate,

wherein the third transistor is provided between the column driver and the second transistor.

16. The semiconductor memory device according to claim 14, further comprising a wiring electrically connected to the back gate of the second transistor,

wherein the wiring is in a floating state.

17. The semiconductor memory device according to claim 14,

wherein the memory cell further comprises a third transistor, and

wherein the drain of the first transistor is electrically connected to a gate of the third transistor.

18. The semiconductor memory device according to claim 14, wherein a minimum potential of the bit line is higher than the minimum potential of the word line by 1 V or more.

19. The semiconductor memory device according to claim 14, further comprising one or more sense amplifiers inserted in the bit line.

20. The semiconductor memory device according to claim 14, further comprising a circuit configured to control a gate of the second transistor.

21. The semiconductor memory device according to claim 14, wherein a maximum potential of the gate of the second transistor is higher than a maximum potential of the word line by 1 V or more.

22. The semiconductor memory device according to claim 14, wherein the potential of the back gate of the second transistor is lower than a potential of any other portion.

23. The semiconductor memory device according to claim 14, wherein each of the first transistor and the second transistor comprises a semiconductor with an irreversible conductivity type.

24. The semiconductor memory device according to claim 14, wherein each of the first transistor and the second transistor comprises an oxide semiconductor.

25. The semiconductor memory device according to claim 14, wherein each of the first transistor and the second transistor comprises a semiconductor with a bandgap of 2.5 electron volts or more.

26. The semiconductor memory device according to claim 14, wherein the back gate of the second transistor is electrically connected to a negative electrode of a battery.