SEMICONDUCTOR MEMORY DEVICE
First Claim
1. A semiconductor memory device comprising:
- a column driver;
a bit line;
a word line;
a memory cell comprising a first transistor and a capacitor; and
a second transistor including a back gate,wherein a source of the first transistor is electrically connected to the bit line,wherein a drain of the first transistor is electrically connected to one electrode of the capacitor,wherein a gate of the first transistor is electrically connected to the word line,wherein a drain of the second transistor is electrically connected to the bit line,wherein a source of the second transistor is electrically connected to the column driver, andwherein a potential of the back gate of the second transistor is lower than a minimum potential of the word line.
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Accused Products
Abstract
An object is to increase the retention characteristics of a memory device formed using a semiconductor with a wide bandgap, such as an oxide semiconductor. A transistor including a back gate (a back gate transistor) is inserted in series at one end of a bit line so that the back gate is constantly at a sufficiently negative potential. The minimum potential of the bit line is set higher than that of a word line. When power is turned off, the bit line is cut off by the back gate transistor, ensuring prevention of outflow of charge accumulated in the bit line. At this time, the potential of a source or a drain (bit line) of a cell transistor is sufficiently higher than that of a gate of the cell transistor (0 V), so that the cell transistor is put in a sufficiently off state; thus, data can be retained.
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Citations
26 Claims
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1. A semiconductor memory device comprising:
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a column driver; a bit line; a word line; a memory cell comprising a first transistor and a capacitor; and a second transistor including a back gate, wherein a source of the first transistor is electrically connected to the bit line, wherein a drain of the first transistor is electrically connected to one electrode of the capacitor, wherein a gate of the first transistor is electrically connected to the word line, wherein a drain of the second transistor is electrically connected to the bit line, wherein a source of the second transistor is electrically connected to the column driver, and wherein a potential of the back gate of the second transistor is lower than a minimum potential of the word line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A semiconductor memory device comprising:
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a column driver; a bit line; a word line; a memory cell comprising a first transistor and a capacitor; and a second transistor including a back gate, wherein a source of the first transistor is electrically connected to the bit line, wherein a drain of the first transistor is electrically connected to one electrode of the capacitor, wherein a gate of the first transistor is electrically connected to the word line, wherein the bit line is electrically connected to the column driver, wherein the second transistor is inserted in series in the bit line, and wherein a potential of the back gate of the second transistor is lower than a minimum potential of the word line. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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Specification