SEMICONDUCTOR DEVICE

• US 20120314524A1
• Filed: 05/24/2012
• Published: 12/13/2012
• Est. Priority Date: 06/10/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Takemura, Yasuhiko
• Granted Patent: US 8,958,263 B2
• Time in Patent Office: Days
• US Class Current: 365/230.06
• CPC Class Codes: G11C 11/403 with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 14/0009 in which the volatile element is a DRAM cell
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

An object is to increase the retention characteristics of a memory device formed using a wide bandgap semiconductor. A bit line controlling transistor is inserted in a bit line in series. The minimum potential of a gate of the transistor is set to a sufficiently negative value. The gate of the transistor is connected to a bit line controlling circuit connected to a battery. The minimum potential of the bit line is set higher than that of a word line. When power from an external power supply is interrupted, the bit line is cut off by the transistor, ensuring prevention of outflow of charge in the bit line. The potential of a source or a drain (bit line) of a cell transistor is sufficiently higher than that of a gate of the cell transistor, resulting in an absolute off-state; thus, data can be retained. Other embodiments are disclosed.

Claims

1. A semiconductor device comprising:

a column driver;

a bit line;

a word line;

a memory cell;

a bit line controlling transistor; and

a bit line controlling circuit,

wherein the memory cell includes a transistor and a capacitor,

wherein a source of the transistor is connected to the bit line,

wherein a drain of the transistor is connected to one electrode of the capacitor,

wherein a gate of the transistor is connected to the word line,

wherein a source of the bit line controlling transistor is connected to the bit line,

wherein a drain of the bit line controlling transistor is connected to the column driver,

wherein a gate of the bit line controlling transistor is connected to the bit line controlling circuit, and

wherein the bit line controlling circuit is connected to one electrode of a device configured to independently generate potential.

5. The semiconductor device according to claim 1, wherein the gate of the bit line controlling transistor is connected, via an n-channel transistor in the bit line controlling circuit, to a negative electrode of the device configured to independently generate potential.

6. The semiconductor device according to claim 1, wherein the drain of the transistor is connected to a gate of another transistor.

7. The semiconductor device according to claim 1, wherein a minimum potential of the bit line is higher than a minimum potential of the word line by 1 V or more.

8. The semiconductor device according to claim 1, wherein one or more sense amplifiers are inserted in the bit line.

9. The semiconductor device according to claim 1,

wherein the bit line controlling circuit includes an inverter, and

wherein an output of the inverter is connected to the gate of the bit line controlling transistor.

10. The semiconductor device according to claim 1, wherein a maximum potential of the gate of the bit line controlling transistor is higher than a maximum potential of the word line by 1 V or more.

11. The semiconductor device according to claim 1, wherein the transistor and the bit line controlling transistor are formed using an oxide semiconductor.

12. The semiconductor device according to claim 1, wherein the transistor and the bit line controlling transistor are formed using a semiconductor with a bandgap of 2.5 electron volts or more.

13. The semiconductor device according to claim 1, wherein the device configured to independently generate potential is a battery.

2. A semiconductor device comprising:

a column driver;

a bit line;

a word line;

a memory cell;

a bit line controlling transistor; and

a bit line controlling circuit,

wherein the memory cell includes a transistor and a capacitor,

wherein a source of the transistor is connected to the bit line,

wherein a drain of the transistor is connected to one electrode of the capacitor,

wherein a gate of the transistor is connected to the word line,

wherein the bit line is connected to the column driver,

wherein the bit line has the bit line controlling transistor at one end,

wherein a gate of the bit line controlling transistor is connected to the bit line controlling circuit, and

wherein the bit line controlling circuit is connected to one electrode of a device configured to independently generate potential.

3. A semiconductor device comprising:

a column driver;

a bit line;

a word line;

a memory cell;

a bit line controlling transistor; and

a bit line controlling circuit,

wherein the memory cell includes a transistor and a capacitor,

wherein a source of the transistor is connected to the bit line,

wherein a drain of the transistor is connected to one electrode of the capacitor,

wherein a gate of the transistor is connected to the word line,

wherein the bit line is connected to the column driver,

wherein the bit line controlling transistor is inserted in the bit line in series,

wherein a gate of the bit line controlling transistor is connected to the bit line controlling circuit, and

wherein the bit line controlling circuit is connected to one electrode of a device configured to independently generate potential.

4. The semiconductor device according to claim 3, wherein two or more bit line controlling transistors are inserted in the bit line.

14. A semiconductor device comprising:

a row driver;

a column driver;

a bit line;

a word line; and

a memory cell;

wherein the memory cell includes a transistor and a capacitor,

wherein a source of the transistor is connected to the bit line,

wherein a drain of the transistor is connected to one electrode of the capacitor,

wherein a gate of the transistor is connected to the word line,

wherein a transistor having a source connected to a device configured to independently generate potential is provided at a connecting point between the row driver and the word line.

16. The semiconductor device according to claim 14, wherein the source of the one transistor in the row driver is connected to a negative electrode of the device configured to independently generate potential.

17. The semiconductor device according to claim 14, wherein the drain of the transistor in the memory cell is connected to a gate of another transistor.

18. The semiconductor device according to claim 14, wherein a minimum potential of the bit line is higher than a minimum potential of the word line by 1 V or more.

19. The semiconductor device according to claim 14, wherein the one transistor in the row driver is included in an inverter.

20. The semiconductor device according to claim 14 wherein the one transistor in the row driver is an n-channel transistor.

21. The semiconductor device according to claim 14, wherein the transistor in the memory cell is formed using an oxide semiconductor.

22. The semiconductor device according to claim 14, wherein the transistor in the memory cell is formed using a semiconductor with a bandgap of 2.5 electron volts or more.

23. The semiconductor device according to claim 14, wherein the device configured to independently generate potential is a battery.

15. A semiconductor device comprising:

a row driver;

a column driver;

a bit line;

a word line; and

a memory cell;

wherein the memory cell includes a transistor and a capacitor,

wherein a source of the transistor is connected to the bit line,

wherein a drain of the transistor is connected to one electrode of the capacitor,

wherein a gate of the transistor is connected to the word line,

wherein one transistor in the row driver has a drain connected to the word line, and a source connected to a device configured to independently generate potential.