SYNAPSE FOR FUNCTION CELL OF SPIKE TIMING DEPENDENT PLASTICITY (STDP), FUNCTION CELL OF STDP, AND NEUROMORPHIC CIRCUIT USING FUNCTION CELL OF STDP

• US 20120317063A1
• Filed: 06/07/2012
• Published: 12/13/2012
• Est. Priority Date: 06/08/2011
• Status: Active Grant

• Current Assignee: Postech Academy-Industry Foundation, Samsung Electronics Co. Ltd.
• Original Assignee: Postech Academy-Industry Foundation, Samsung Electronics Co. Ltd.
• Inventors: SIM, Jae Yoon, Ryu, Hyun Surk, Lee, Jun Haeng
• Granted Patent: US 9,087,302 B2
• Time in Patent Office: Days
• US Class Current: 706/27
• CPC Class Codes: G06N 3/049 Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs
• CPC Class Codes: G06N 3/063 using electronic means
• CPC Class Codes: G06N 3/088 Non-supervised learning, e.g. competitive learning
• CPC Class Codes: G11C 11/54 using elements simulating biological cells, e.g. neuron
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 2213/53 Structure wherein the resistive material being in a transistor, e.g. gate
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: G11C 7/16 Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters

Abstract

A synapse for a spike timing dependent (STDP) function cell includes a memory device having a variable resistance, such as a memristor, and a transistor connected to the memory device. A channel of the memory device is connected in series with a channel of the transistor.

Claims

1. A synapse for a spike timing dependent plasticity (STDP) function cell, the synapse comprising:

a memory device having a variable resistance; and

a transistor connected to the memory device;

wherein a channel of the memory device is connected in series with a channel of the transistor.

2. The synapse of claim 1, wherein the resistance of the memory device varies according to a synaptic weight dependent on a voltage difference between voltages applied to both ends of the memory device.

3. The synapse of claim 1, wherein the memory device is connected to a drain terminal of the transistor.

4. The synapse of claim 1, wherein the synapse is configured so that a same voltage can be applied to the memory device and a source terminal of the transistor.

5. The synapse of claim 1, further comprising:

a first terminal connected to the memory device; and

a second terminal connected to a source terminal of the transistor;

wherein the synapse is connected to a pre-synaptic neuron through the first terminal, and connected to a post-synaptic neuron through the second terminal.

6. The synapse of claim 5, wherein the synapse is configured to selectively operate in a communication mode in which the synapse transmits information from the pre-synaptic neuron to the post-synaptic neuron, and a learning mode in which a synaptic weight of the synapse changes in response to a voltage difference between voltages applied to both ends of the memory device;

and

the synapse is configured to switch between the communication mode and the learning mode according to a time division multiplexing (TDM) scheme.

7. The synapse of claim 6, wherein in the communication mode, the synapse transmits the information from the pre-synaptic neuron to the post-synaptic neuron by transmitting a signal generated by a spike fired by the pre-synaptic neuron to the post-synaptic neuron;

and

in the learning mode, the synaptic weight of the synapse changes as a result of the resistance of the memory device changing in response to the voltage difference between the voltages applied to both ends of the memory device.

8. The synapse of claim 6, wherein the synapse is configured to switch to the communication mode by switching the first terminal to connect to a drain voltage (VDD) of the pre-synaptic neuron, and switching the second terminal to connect to a membrane capacitor of the post-synaptic neuron.

9. The synapse of claim 6, wherein the synapse is configured to switch to the learning mode by switching the first terminal to connect to an output of a pulse shaper of the pre-synaptic neuron, and switching the second terminal to connect to an output of a pulse shaper of the post-synaptic neuron.

10. A spike timing dependent plasticity (STDP) function cell having an STDP function for a neuromorphic circuit, the STDP function cell comprising:

a synapse comprising;

a memory device having a variable resistance;

a transistor connected to the memory device;

a first terminal; and

a second terminal;

a pre-synaptic neuron connected to the memory device through the first terminal of the synapse; and

a post-synaptic neuron connected to a source terminal of the transistor through the second terminal of the synapse;

wherein a channel of the memory device is connected in series with a channel of the transistor.

11. The STDP function cell of claim 10, wherein the resistance of the memory device varies according to a synaptic weight dependent on a voltage difference between voltages applied to both ends of the memory device.

12. The STDP function cell of claim 10, wherein the pre-synaptic neuron and the post-synaptic neuron each comprise:

an electronic neuron circuit configured to fire a spike;

a spike time recorder configured to record a point of time when the electronic neuron circuit fires the spike as a digital code; and

a pulse shaper configured to restore a pulse shape of the spike based on the digital code;

wherein the spike time recorder and the pulse shaper are configured to operate in synchronization with a clock.

13. The STDP function cell of claim 12, wherein the pulse shaper comprises a discrete time finite impulse response (FIR) filter configured to sequentially shift the digital code and sum the shifted digital to restore the pulse shape of the spike.

14. The STDP function cell of claim 12, wherein the STDP function cell is configured to selectively operate in a communication mode in which the synapse transmits information from the pre-synaptic neuron to the post-synaptic neuron, and a learning mode in which a synaptic weight of the synapse changes in response to a voltage difference between voltages applied to both ends of the memory device;

and

the STDP function cell is configured to switch between the communication mode and the learning mode according to a time division multiplexing (TDM) scheme.

15. The STDP function cell of claim 14, wherein the STDP function cell is configured to switch to the communication mode by switching the first terminal to connect to a drain voltage (VDD) of the pre-synaptic neuron, and switching the second terminal to connect to a membrane capacitor of the post-synaptic neuron.

16. The STDP function cell of claim 14, wherein the STDP function cell is configured to switch to the learning mode by switching the first terminal to connect to an output of the pulse shaper of the pre-synaptic neuron, and switching the second terminal to connect to an output of the pulse shaper of the post-synaptic neuron.

17. The STDP function cell of claim 14, wherein an impedance of the synapse when the STDP function cell is not operating in the communication mode and is not operating in the learning mode is higher than an impedance of the synapse when the STDP function cell is operating in the communication mode and is operating in the learning mode.

18. A neuromorphic circuit comprising a plurality of spike timing dependent plasticity (STDP) function cells, the neuromorphic circuit comprising:

a plurality of synapses arranged in a crossbar structure, each of the synapses comprising;

a memory device having a variable resistance; and

a transistor connected to the memory device;

a plurality of pre-synaptic neurons each connected to a respective column of the crossbar structure; and

a plurality of post-synaptic neurons each connected to a respective row of the crossbar structure;

wherein ones of the synapses arranged in a same row of the crossbar structure are all connected to the post-synaptic neuron connected to that row, and are each connected to the pre-synaptic neuron connected to a respective column of the crossbar structure;

ones of the synapses arranged in a same column of the crossbar structure are all connected to the pre-synaptic neuron connected to that column, and are each connected to the post-synaptic neuron connected to a respective row of the crossbar structure;

each of the STDP function cells comprises one of the synapses, one of the pre-synaptic neurons, and one of the post-synaptic neurons; and

in each of the synapses, a channel of the memory device is connected in series with a channel of the transistor.

19. The neuromorphic circuit of claim 18, wherein the resistance of the memory device varies according to a synaptic weight dependent on a voltage difference between voltages applied to both ends of the memory device.

20. The neuromorphic circuit of claim 18, wherein each of the STDP function cells is configured to selectively operate in a communication mode in which the synapse transmits information from the pre-synaptic neuron to the post-synaptic neuron, and a learning mode in which a synaptic weight of the synapse changes in response to a voltage difference between voltages applied to both ends of the memory device;

and

each of the STDP function cells is configured to switch between the communication mode and the learning mode according to a time division multiplexing (TDM) scheme.

21. A synapse for a spike timing dependent plasticity (STDP) function cell, the synapse comprising:

a first synapse terminal;

a second synapse terminal;

a synapse control terminal;

a memory device having a variable resistance and comprising a first terminal and a second terminal; and

a transistor comprising a first terminal, a second terminal, and a control terminal that controls a flow of current between the first terminal of the transistor and the second terminal of the transistor;

wherein the first terminal of the memory device is connected to the first synapse terminal;

the second terminal of the memory device is connected to the first terminal of the transistor;

the second terminal of the transistor is connected to the second synapse terminal; and

the control terminal of the transistor is connected to the synapse control terminal.

22. The synapse of claim 21, wherein the resistance of the memory device determines a synaptic weight of the synapse, and depends on a voltage difference between a first voltage that was last applied to the first terminal of the memory device during a last learning mode of the synapse and a second voltage that was last applied to the second terminal of the memory device during the last learning mode of the synapse.

23. The synapse of claim 21, wherein the resistance of the memory device determines a synaptic weight of the synapse, and depends on a timing between a first neuron spike that was last applied to the first terminal of the memory device during a last learning mode of the synapse and a second neuron spike that was last applied to the second terminal of the memory device during the last learning mode of the synapse.

24. The synapse of claim 21, wherein the resistance of the memory device determines a synaptic weight of the synapse, and changes in accordance with an STDP function in response to a voltage difference between a voltage of a first neuron spike applied to the first terminal of the memory device during a learning mode of the memory device and a voltage of a second neuron spike applied to the second terminal of the memory device during the learning mode of the memory device.

25. The synapse of claim 24, wherein the voltage difference depends on a difference between a time at which the first neuron spike is fired and a time at which the second neuron spike is fired.

26. The synapse of claim 25, wherein the first neuron spike is a pre-synaptic neuron spike;

the second neuron spike is a post-synaptic neuron spike;

the resistance of the memory device decreases if the post-synaptic neuron spike is fired after the pre-synaptic neuron spike is fired, thereby increasing the synaptic weight of the synapse; and

the resistance of the memory device increases if the post-synaptic neuron spike is fired before the pre-synaptic neuron spike is fired, thereby decreasing the synaptic weight of the synapse.

27. The synapse of claim 21, wherein the transistor further comprises a channel connected between the first terminal of the transistor and the second terminal of the transistor;

and

the control terminal of the transistor is a gate terminal of the transistor.

28. The synapse of claim 27, wherein the first terminal of the transistor is a drain terminal of the transistor;

and

the second terminal of the transistor is a source terminal of the transistor.

29. The synapse of claim 21, wherein a current cannot flow between the first terminal of the synapse and the second terminal of the synapse when the control terminal of the transistor turns the transistor off so that current cannot flow between the first terminal of the transistor and the second terminal of the transistor.

30. A spike timing dependent plasticity (STDP) function cell comprising:

a synapse comprising a first synapse terminal, a second synapse terminal, and a synapse control terminal;

a pre-synaptic neuron connected to the first synapse terminal; and

a post-synaptic neuron connected to the second synapse terminal;

wherein the synapse further comprises;

a memory device having a variable resistance and comprising a first terminal and a second terminal; and

a transistor comprising a first terminal, a second terminal, and a control terminal that controls a flow of current between the first terminal of the transistor and the second terminal of the transistor;

the first terminal of the memory device is connected to the first synapse terminal;

the second terminal of the memory device is connected to the first terminal of the transistor;

the second terminal of the transistor is connected to the second synapse terminal; and

the control terminal of the transistor is connected to the synapse control terminal.

31. The STDP function cell of claim 30, wherein the pre-synaptic neuron and the post-synaptic neuron each comprise:

an electronic neuron circuit configured to fire a neuron spike;

a spike time recorder configured to receive the neuron spike from the electronic neuron circuit and record a firing time point of the neuron spike as a digital code; and

a pulse shaper configured to receive the digital code from the spike time recorder and output a voltage pulse having a shape of the neuron spike in response to the digital code;

the pre-synaptic neuron further comprises;

a first voltage supply terminal; and

a second voltage supply terminal;

the post-synaptic neuron further comprises a capacitor;

in a communication mode of the STDP function cell, the first synapse terminal is connected to the first voltage supply terminal of the pre-synaptic neuron, the second synapse terminal is connected to the capacitor of the post-synaptic neuron, and the synapse control terminal receives the neuron spike fired by the electronic neuron circuit of the pre-synaptic neuron; and

in a learning mode of the STDP function cell, the first synapse terminal receives the voltage pulse output by the pulse shaper of the pre-synaptic neuron, the second synapse terminal receives the voltage pulse output by the pulse shaper of the post-synaptic neuron, and the synapse control terminal is connected to the second voltage supply terminal of the pre-synaptic neuron.