Cache Streaming System

• US 20120317360A1
• Filed: 05/16/2012
• Published: 12/13/2012
• Est. Priority Date: 05/18/2011
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Lantiq Deutschland GMBH (Intel Corporation)
• Inventors: Zettler, Thomas, Fenzl, Gunther, Wachendorf, Olaf, Thudt, Raimar, Banerjee, Ritesh
• Application Number:
  US13/472,569
• Publication Number:
  US 20120317360A1
• Time in Patent Office: Days
• US Class Current: 711/122
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass

Abstract

A system, having a stream cache and a storage. The stream cache includes a stream cache controller adapted to control or mediate input data transmitted through the stream cache; and a stream cache memory. The stream cache memory is adapted to both store at least first portions of the input data, as determined by the stream cache controller, and to further output the stored first portions of the input data to a processor. The storage is adapted to receive and store second portions of the input data, as determined by the stream cache controller, and to further transmit the stored second portions of the input data for output to the processor.

Claims

1. A system, comprising:

a stream cache and a storage, wherein the stream cache includes;

a stream cache controller adapted to control transmission of input data through the stream cache; and

a stream cache memory, the stream cache memory being adapted;

to store at least first portions of the input data, as determined by the stream cache controller, and

to further output the stored first portions of the input data to a processor; and

wherein the storage is adapted;

to receive and store second portions of the input data, as determined by the stream cache controller, and

to further transmit the stored second portions of the input data for output to the processor.

2. The system according to claim 1, wherein the storage is adapted to further transmit the stored second portions to the stream cache memory.

3. The system according to claim 1, wherein the input data is received wirelessly.

4. The system according to claim 1, wherein the system is implemented in at least one of a WAN, DSL or PON system.

5. The system according to claim 1, wherein the system conforms at least in part to the G.hn standard.

6. The system as claimed in claim 1, wherein transmission of the stored second portions is to the stream cache memory for output to the processor.

7. The system according to claim 1, further comprising an input buffer from which the stream cache is adapted to receive the input data.

8. The system according to claim 1, wherein the stream cache controller is adapted to control the transmission of the input data through the stream cache by mediating the input data through the stream cache based on formatting of the input data.

9. The system according to claim 1, wherein the stream cache controller is adapted to mediate the input data through the stream cache based on priority of a stream of the input data.

10. The system according to claim 1, wherein the stream cache controller is adapted to control the transmission of the input data through the stream cache by mediating the input data through the stream cache based on pointers of the portions of the input data stored on the stream cache memory.

11. The system according to claim 10, wherein the stream cache controller further determines to store the other portions of the input data on the storage.

12. The system according to claim 1, adapted for use with input data wherein the first portions of the input data stored on the stream cache memory are data packet headers and wherein the second portions of the input data stored on the storage are data packet bodies.

13. The system according to claim 7, further comprising a merger unit adapted to merge the data packet headers with the respective data packet bodies.

14. The system according to claim 1, adapted to store, on the stream cache memory, data packets included in the first portions of the input data on a first-in basis, and adapted to store, on the storage, data packets of the second portions of the input data.

15. The system according to claim 12, wherein the input data is data most recently received by the stream cache from an input buffer.

16. The system according to claim 1, wherein the storage is provided by a level-two cache.

17. The system according to claim 1, wherein the storage is provided by an external memory.

18. The system according to claim 1, wherein the storage is adapted to transmit the stored second portions of the input data to the stream cache memory on a first-in first-out basis at a time determined by the stream cache controller.

19. The system according to claim 18, wherein the storage is adapted to transmit the stored second portions of the input data to the stream cache memory on a first-in first-out basis based on formatting thereof as instructed by the stream cache controller.

20. A non-volatile computer-readable medium on which at least one instruction is stored that, when executed, cause at least one processor:

to determine first portions of an input data stream to be stored locally on a cache memory and second portions of the input data stream to be stored on a different storage;

to store pointers to the first portions of the input data stream that are stored locally on the cache memory; and

to fetch the second portions of the input data stream that are stored on the different storage based on a specified criterion.

21. The non-volatile computer-readable medium according to claim 20, wherein the at least one instruction, when executed, causes the at least one processor to determine to include at least one of:

determining to store data packets on the cache memory on a first-in basis and to store data packets on the different storage when the cache memory is at capacity;

determining to store first level priority data packets on the cache memory and to store second level priority data packets on the different storage;

fetching the second portions of the data stream that are stored on the different storage to the cache memory as the first portions of the input data stream stored on the cache memory are output to the data processing engine;

determining to store data packet headers on the cache memory and to store corresponding data packet bodies on the different storage; and

merging the data packet headers with the corresponding data packet bodies after the respective data packet headers have been processed by the data processing engine.

22. The non-volatile computer-readable medium according to claim 21, wherein the at least one instruction, when executed, causes the at least one processor to fetch or include fetching the second portions of the data stream that are stored on the different storage to the cache memory on a first-in first-out basis.

23. The non-volatile computer-readable medium according to claim 22, wherein the at least one instruction, when executed, causes the at least one processor to fetch from the different storage.