SATISFYING MEMORY ORDERING REQUIREMENTS BETWEEN PARTIAL READS AND NON-SNOOP ACCESSES
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Abstract
A method and apparatus for preserving memory ordering in a cache coherent link based interconnect in light of partial and non-coherent memory accesses is herein described. In one embodiment, partial memory accesses, such as a partial read, is implemented utilizing a Read Invalidate and/or Snoop Invalidate message. When a peer node receives a Snoop Invalidate message referencing data from a requesting node, the peer node is to invalidate a cache line associated with the data and is not to directly forward the data to the requesting node. In one embodiment, when the peer node holds the referenced cache line in a Modified coherency state, in response to receiving the Snoop Invalidate message, the peer node is to writeback the data to a home node associated with the data.
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Citations
27 Claims
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1-7. -7. (canceled)
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8. An apparatus comprising:
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receiving logic to receiving a snoop invalidate message referencing data; a cache memory including a cache line to hold the data; and protocol logic coupled to the receiving logic and the cache memory, the protocol logic, in response to the receiving logic receiving the snoop invalidate message referencing the data and the cache line being held in a first cache coherency state, to generate a writeback of the data to a home node associated with the data and to initiate a transition of the cache line from the first cache coherency state to an invalid cache coherency state. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A system comprising:
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a first peer node to implement a first interconnect stack including a first protocol layer to generate a first message and a second message referencing a data element, and a first physical layer to transmit the first message to a home node and the second message to a second peer node; wherein the second peer node is to be coupled to the first peer node through a point-to-point link, the second peer node to include a cache memory to hold a cached copy of the data element and to implement a second interconnect stack including a second physical layer to receive the second message and a second protocol layer to not forward the cached copy of the data element directly to the first peer node and to cause the cached copy of the data element to be transitioned to an Invalid coherency state in response to the second physical layer receiving the second message; and wherein the home node is to be coupled to the first peer node through a point-to-point link and is to implement a third interconnect stack including a third physical layer to receive the first message and a third protocol layer to generate a data message to provide a correct copy of the data element to the first peer node in response to the third physical layer receiving the first message. - View Dependent Claims (16, 17, 18, 19, 20)
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21. A method comprising:
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generating a first message referencing data with a requesting node; receiving the first message referencing data with a peer node; and not directly forwarding a copy of the data held in a cache line of a cache memory in the peer node to the requesting node and invalidating the cache line, in response to receiving the first message with the peer node. - View Dependent Claims (22, 23, 24, 25, 26, 27)
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Specification