DATA STORAGE SYSTEM WITH POWER CYCLE MANAGEMENT AND METHOD OF OPERATION THEREOF

• US 20120317433A1
• Filed: 06/11/2012
• Published: 12/13/2012
• Est. Priority Date: 06/13/2011
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Smart Storage Systems Incorporated (Western Digital Corporation)
• Inventors: Ellis, Robert W., Creasman, Scott
• Granted Patent: US 8,792,273 B2
• Time in Patent Office: Days
• US Class Current: 713/340
• CPC Class Codes: G06F 11/1441 Resetting or repowering

Abstract

A method of operation of a data storage system includes: providing a power monitor module for detecting a loss of host power; interrupting a unit controller by the power monitor module; configuring a memory controller by the unit controller; and writing a non-volatile memory array for storing in-flight data and contents of a system control random access memory in a multi-level cell NAND flash device in response to detecting the loss of the host power.

Claims

1. A method of operation of a data storage system comprising:

providing a power monitor module for detecting a loss of host power;

interrupting a unit controller by the power monitor module;

configuring a memory controller by the unit controller; and

writing a non-volatile memory array for storing in-flight data and contents of a system control random access memory in a multi-level cell NAND flash device in response to detecting the loss of the host power.

2. The method as claimed in claim 1 wherein writing the non-volatile memory array includes writing only fast pages of the multi-level cell NAND flash device.

3. The method as claimed in claim 1 further comprising writing a first non-volatile memory segment, a second non-volatile memory segment, and an Nth non-volatile memory segment forming the non-volatile memory array.

4. The method as claimed in claim 1 further comprising pre-assigning an erase block for writing the contents of the system control random access memory.

5. The method as claimed in claim 1 wherein configuring the memory controller by the unit controller includes selecting a first storage channel for the in-flight data and an Nth storage channel for the contents of a system control random access memory.

6. A method of operation of a data storage system comprising:

providing a power monitor module for detecting a loss of host power through a storage system interface;

interrupting a unit controller by the power monitor module including activating a hold-up power in the power monitor module;

configuring a memory controller by the unit controller including communicating through a storage bus; and

writing a non-volatile memory array for storing in-flight data and the contents of the system control random access memory in response to detecting the loss of the host power including writing only fast pages of a multi-level cell NAND flash device through an Nth storage channel.

7. The method as claimed in claim 6 wherein writing only the fast pages of the multi-level cell NAND flash device includes writing the in-flight data to a first non-volatile memory segment while concurrently writing the contents of the system control random access memory to an Nth non-volatile memory segment.

8. The method as claimed in claim 6 further comprising writing a first non-volatile memory segment, a second non-volatile memory segment, and an Nth non-volatile memory segment forming the non-volatile memory array including activating a first storage channel, a second storage channel, and an Nth storage channel.

9. The method as claimed in claim 6 further comprising pre-assigning an erase block for writing the contents of the system control random access memory including writing system pointers to the erase block for a subsequent restoration of the host power.

10. The method as claimed in claim 6 wherein configuring the memory controller by the unit controller includes selecting a first storage channel for the in-flight data and an Nth storage channel for the contents of a system control random access memory for concurrent transferring the in-flight data and the content of the system control random access memory.

11. A data storage system comprising:

a power monitor module for detecting a loss of a host power;

a unit controller coupled to the power monitor module for responding to the loss of the host power detected;

a memory controller coupled to the unit controller; and

a non-volatile memory array coupled to the memory controller for storing the in-flight data and contents of a system control random access memory includes writing only fast pages of a multi-level cell NAND flash device.

12. The system as claimed in claim 11 further comprising a volatile memory bus between the memory controller and the system control random access memory.

13. The system as claimed in claim 11 wherein the non-volatile memory array includes a first non-volatile memory segment, a second non-volatile memory segment, and an Nth non-volatile memory segment.

14. The system as claimed in claim 11 further comprising an erase block pre-assigned for storing the contents of a system control random access memory.

15. The system as claimed in claim 11 further comprising a primary storage bus between the memory controller and the non-volatile memory array.

16. The system as claimed in claim 11 further comprising:

a storage system interface coupled to the power monitor module for receiving the host power and the in-flight data; and

slow pages in a first Nth non-volatile memory segment and the Nth non-volatile memory segment skipped by the memory controller.

17. The system as claimed in claim 16 further comprising a volatile memory bus between the memory controller and the system control random access memory includes the contents of the system control random access memory coupled through the memory controller to the Nth non-volatile memory segment.

18. The system as claimed in claim 16 wherein the non-volatile memory array includes a first storage channel coupled to the first non-volatile memory segment, a second storage channel coupled to the second non-volatile memory segment, and an Nth storage channel coupled to the Nth non-volatile memory segment.

19. The system as claimed in claim 16 further comprising an erase block pre-assigned for storing the contents of a system control random access memory includes system pointers pre-written to the erase block for a subsequent restoration of the host power.

20. The system as claimed in claim 16 further comprising a primary storage bus between the memory controller and the non-volatile memory array and the memory controller having a first storage channel for the in-flight data and an Nth storage channel for the contents of a system control random access memory for concurrently transferring the in-flight data and the content of the system control random access memory.