Method and Apparatus for N+1 Packet Level Mesh Protection

• US 20120317456A1
• Filed: 08/22/2012
• Published: 12/13/2012
• Est. Priority Date: 09/29/2005
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Langner, Paul
• Granted Patent: US 8,745,461 B2
• Time in Patent Office: Days
• US Class Current: 714/752
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 1/0061 Error detection codes

Abstract

Methods and apparatus are provided for N+1 packet level mesh protection. An error correction encoder is provided for encoding message symbols, m0 through mN−1, to generate a codeword that includes the message symbols, m0 through mN−1, and one or more check symbols. The error correction encoder comprises a linear feedback shift register having one or more flip-flops to generate the check symbols after shifting the message symbols, m0 through mN−1, through the linear feedback shift register. An error correction decoder is also provided for decoding a codeword that includes message symbols, m0 through mN−1, and one or more check symbols. The error correction decoder comprises a linear feedback shift register having one or more flip-flops to generate an error symbol based on a remainder after shifting the message symbols, m0 through mN−1, and the one or more check symbols through the linear feedback shift register.

Claims

1. An error correction encoder for encoding message symbols, m₀ through m_N−

1, to generate a codeword that includes said message symbols, m₀ through m<sub>N−

1</sub>, and one or more check symbols, comprising;

a linear feedback shift register having one or more flip-flops to generate said check symbols after shifting said message symbols, m₀ through m<sub>N−

1</sub>, through said linear feedback shift register.

2. The error correction encoder of claim 1, wherein a payload containing said message symbols, m₀ through m_N−

1, comprises a symbol-wise exclusive or (XOR) of said message symbols, m₀ through m<sub>N−

1</sub>.

3. An error correction decoder for decoding a codeword that includes message symbols, m₀ through m_N−

1, and one or more check symbols, comprising;

a linear feedback shift register having one or more flip-flops to generate an error symbol based on a remainder after shifting said message symbols, m₀ through <sub>n−

1</sub>, and said one or more check symbols through said linear feedback shift register.

4. The error correction decoder of claim 3, wherein said error symbol is said remainder for T equal to one check symbol.