SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

• US 20120319113A1
• Filed: 05/31/2012
• Published: 12/20/2012
• Est. Priority Date: 06/17/2011
• Status: Abandoned Application

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: YAMAZAKI, Shunpei
• Application Number:
  US13/484,740
• Publication Number:
  US 20120319113A1
• Time in Patent Office: Days
• US Class Current: 257/57
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

At least part of the oxide semiconductor layer which serves as the channel formation region is thinned by etching and the thickness of the channel formation region is adjusted by the etching. Further, a dopant containing phosphorus (P) or boron (B) is introduced into a thick region of the oxide semiconductor layer to form a source region and a drain region in the oxide semiconductor layer, so that the contact resistance between the source and drain regions and the channel formation region which are connected to each other is reduced.

Claims

1. A semiconductor device comprising:

an oxide semiconductor layer over an insulating surface, wherein the oxide semiconductor layer including a first region and a pair of second regions with the first region interposed therebetween;

a gate insulating layer over the oxide semiconductor layer; and

a gate electrode layer over the gate insulating layer,

wherein a source region and a drain region are formed in the pair of second regions,

wherein the first region is thinner than the pair of second regions and

wherein the first region includes a channel formation region overlapping with the gate electrode layer.

2. The semiconductor device according to claim 1, wherein an end portion of the first region is aligned with an end portion of the gate electrode layer.

3. The semiconductor device according to claim 1, further comprising:

a protective layer over the gate electrode layer; and

a wiring layer over the protective layer, wherein the wiring layer is electrically in contact with the source region and the drain region.

4. The semiconductor device according to claim 1, further comprising a metal layer electrically in contact with the source region and the drain region.

5. The semiconductor device according to claim 4, wherein an end portion of the metal layer is aligned with an end portion of the pair of second regions.

6. The semiconductor device according to claim 4, wherein an end portion of the metal layer is on an inner side than an end portion of the pair of second regions.

7. The semiconductor device according to claim 1, wherein the source region and the drain region include phosphorus or boron.

8. The semiconductor device according to claim 1, wherein the insulating surface is an oxide insulating surface.

9. A semiconductor device comprising:

an oxide semiconductor layer over an insulating surface, wherein the oxide semiconductor layer including a first region and a pair of second regions with the first region interposed therebetween;

a gate insulating layer over the oxide semiconductor layer; and

a gate electrode layer over the gate insulating layer,

wherein a source region and a drain region are formed in the pair of second regions, and

wherein the first region is thinner than the pair of second regions,

wherein the first region includes a channel formation region and a low-resistance region having lower resistance than the channel formation region,

wherein the channel formation region overlaps with the gate electrode layer, and

wherein the low-resistance region includes phosphorus or boron.

10. The semiconductor device according to claim 9, further comprising:

a protective layer over the gate electrode layer; and

a wiring layer over the protective layer, wherein the wiring layer is electrically in contact with the source region and the drain region.

11. The semiconductor device according to claim 9, further comprising a metal layer electrically in contact with the source region and the drain region.

12. The semiconductor device according to claim 11, wherein an end portion of the metal layer is aligned with an end portion of the pair of second regions.

13. The semiconductor device according to claim 11, wherein an end portion of the metal layer is on an inner side than an end portion of the pair of second regions.

14. The semiconductor device according to claim 9, wherein the source region and the drain region include phosphorus or boron.

15. The semiconductor device according to claim 9, wherein the insulating surface is an oxide insulating surface.

16. A method for manufacturing a semiconductor device comprising the steps of:

forming an oxide semiconductor layer over an insulating surface;

forming a mask over the oxide semiconductor layer;

selectively etching the oxide semiconductor layer with the use of the mask to form a first region and a pair of second regions in the oxide semiconductor layer with the first region interposed between the pair of second regions, wherein the first region is thinner than the pair of second regions;

forming a gate insulating layer over the oxide semiconductor layer; and

forming a gate electrode layer overlapping with the first region over the gate insulating layer.

17. The method for manufacturing a semiconductor device according to claim 16, further comprising the step of:

introducing phosphorus or boron into the oxide semiconductor layer through the gate insulating layer, with the use of the gate electrode layer as a mask to form a source region and a drain region in part of the oxide semiconductor layer.

18. The method for manufacturing a semiconductor device according to claim 16, wherein oxygen is introduced into the oxide semiconductor layer through the gate insulating layer after the gate insulating layer is formed.

19. The method for manufacturing a semiconductor device according to claim 16, wherein the insulating surface is an oxide insulating surface.

20. A method for manufacturing a semiconductor device comprising the steps of:

forming a stack of an oxide semiconductor layer and a metal layer over an insulating surface;

forming a mask over the metal layer;

removing part of the metal layer with the use of the mask;

selectively etching the oxide semiconductor layer with the use of the metal layer as a mask to form a first region and a pair of second regions in the oxide semiconductor layer with the first region interposed between the pair of second regions,

wherein the first region is thinner than the pair of second regions;

forming a gate insulating layer over the metal layer and the oxide semiconductor layer; and

forming a gate electrode layer overlapping with the first region, over the gate insulating layer.

21. The method for manufacturing a semiconductor device according to claim 20, further comprising the step of:

introducing phosphorus or boron into the oxide semiconductor layer through the gate insulating layer and the metal layer, with the use of the gate electrode layer as a mask to form a source region and a drain region in part of the oxide semiconductor layer.

22. The method for manufacturing a semiconductor device according to claim 20, wherein oxygen is introduced into the oxide semiconductor layer through the gate insulating layer after the gate insulating layer is formed.

23. The method for manufacturing a semiconductor device according to claim 20, wherein the insulating surface is an oxide insulating surface.