SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

• US 20120319114A1
• Filed: 06/13/2012
• Published: 12/20/2012
• Est. Priority Date: 06/17/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: YAMAZAKI, Shunpei, HONDA, Tatsuya
• Granted Patent: US 9,166,055 B2
• Time in Patent Office: Days
• US Class Current: 257/57
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A transistor including an oxide semiconductor layer and having electric characteristics required depending on an intended use, and a semiconductor device including the transistor are provided. In a transistor in which a semiconductor layer, a source electrode layer and a drain electrode layer, a gate insulating film, and a gate electrode layer are stacked in this order over an oxide insulating film, an oxide semiconductor stack composed of at least two oxide semiconductor layers having different energy gaps is used as the semiconductor layer. Oxygen and/or a dopant may be introduced into the oxide semiconductor stack.

Claims

1. A semiconductor device comprising:

an oxide semiconductor stack comprising a first oxide semiconductor layer and a second oxide semiconductor layer;

a source electrode layer and a drain electrode layer over the oxide semiconductor stack;

an insulating film over the source electrode layer and the drain electrode layer; and

a gate electrode layer over the insulating film, the gate electrode layer overlapping with the oxide semiconductor stack,

wherein energy gaps of the first oxide semiconductor layer and the second oxide semiconductor layer are different from each other.

2. The semiconductor device according to claim 1, wherein the first oxide semiconductor layer and the second oxide semiconductor layer are in contact with the source electrode layer and the drain electrode layer.

3. The semiconductor device according to claim 1, wherein the first oxide semiconductor layer is in contact with the insulating film.

4. The semiconductor device according to claim 1,

wherein the first oxide semiconductor layer includes a channel formation region, a first impurity region, and a second impurity region, and

wherein the channel formation region is interposed between the first impurity region and the second impurity region.

5. The semiconductor device according to claim 4,

wherein the first oxide semiconductor layer further includes a third impurity region,

wherein the first impurity region is interposed between the channel formation region and the third impurity region, and

wherein an impurity concentration of the first impurity region is higher than that of the third impurity region.

6. The semiconductor device according to claim 5,

wherein the third impurity region is overlapped with one of the source electrode layer and the drain electrode layer.

7. A semiconductor device comprising:

an oxide semiconductor stack comprising a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer;

a source electrode layer and a drain electrode layer over the oxide semiconductor stack;

an insulating film over the source electrode layer and the drain electrode layer; and

a gate electrode layer over the insulating film, the gate electrode layer overlapping with the oxide semiconductor stack,

wherein the second oxide semiconductor layer is interposed between the first oxide semiconductor layer and the third oxide semiconductor layer, and

wherein an energy gap of the second oxide semiconductor layer is smaller than energy gaps of the first oxide semiconductor layer and the third oxide semiconductor layer.

8. The semiconductor device according to claim 7, wherein the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer are in contact with the source electrode layer and the drain electrode layer.

9. The semiconductor device according to claim 7, wherein the first oxide semiconductor layer is in contact with the insulating film.

10. The semiconductor device according to claim 7,

wherein the first oxide semiconductor layer includes a channel formation region, a first impurity region, and a second impurity region, and

wherein the channel formation region is interposed between the first impurity region and the second impurity region.

11. The semiconductor device according to claim 10,

wherein the first oxide semiconductor layer further includes a third impurity region,

wherein the first impurity region is interposed between the channel formation region and the third impurity region, and

wherein an impurity concentration of the first impurity region is higher than that of the third impurity region.

12. The semiconductor device according to claim 11,

wherein the third impurity region is overlapped with one of the source electrode layer and the drain electrode layer.

13. The semiconductor device according to claim 7,

wherein the energy gaps of the first oxide semiconductor layer and the third oxide semiconductor layer are substantially the same.

14. The semiconductor device according to claim 7, wherein an electron affinity of the second oxide semiconductor layer is higher than electron affinities of the first oxide semiconductor layer and the third oxide semiconductor layer.

15. A method for manufacturing a semiconductor device, comprising the steps of:

forming an oxide insulating film over a substrate;

forming a first oxide semiconductor film over the oxide insulating film;

forming a second oxide semiconductor film over the first oxide semiconductor film;

forming a third oxide semiconductor film over the second oxide semiconductor film;

forming a first mask over the third oxide semiconductor film;

etching the first oxide semiconductor film, the second oxide semiconductor film, and the third oxide semiconductor film with use of the first mask to form an oxide semiconductor stack;

forming a source electrode layer and a drain electrode layer over the oxide semiconductor stack;

forming an insulating film over the oxide semiconductor stack, the source electrode layer, and the drain electrode layer; and

forming a gate electrode layer over the insulating film,

wherein an energy gap of the second oxide semiconductor film is smaller than energy gaps of the first oxide semiconductor film and the third oxide semiconductor film.

16. The method according to claim 15, wherein heat treatment is performed before the first mask is formed to release hydrogen or moisture included in at least one of the first oxide semiconductor film, the second oxide semiconductor film, and the third oxide semiconductor film.

17. The method according to claim 15, further comprising the step of introducing a dopant into the oxide semiconductor stack in a self-aligned manner with use of the gate electrode layer as a second mask.

18. The method according to claim 15, wherein the oxide insulating film is formed over a semiconductor substrate provided with a transistor.

19. The method according to claim 15,

wherein the energy gaps of the first oxide semiconductor film and the third oxide semiconductor film are substantially the same.

20. The method according to claim 15, wherein an electron affinity of the second oxide semiconductor film is higher than electron affinities of the first oxide semiconductor film and the third oxide semiconductor film.