NONVOLATILE SEMICONDUCTOR MEMORY DEVICE, THREE-DIMENSIONAL SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SAME

• US 20120319173A1
• Filed: 11/17/2011
• Published: 12/20/2012
• Est. Priority Date: 06/15/2011
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: YAHASHI, Katsunori, KO, Nikka
• Granted Patent: US 8,648,404 B2
• Time in Patent Office: Days
• US Class Current: 257/211
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/50 characterised by the boundary region between the core region and the peripheral circuit region
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A three-dimensional semiconductor device includes a semiconductor substrate, a plurality of conductive layers and insulating layers, and a plurality of contacts. The plurality of conductive layers and insulating layers are stacked alternately above the semiconductor substrate. The plurality of contacts extend in a stacking direction of the plurality of conductive layers and insulating layers. The plurality of conductive layers form a stepped portion having positions of ends of the plurality of conductive layers gradually shifted from an upper layer to a lower layer. The plurality of contacts are connected respectively to each of steps of the stepped portion. The stepped portion is formed such that, at least from an uppermost conductive layer to a certain conductive layer, the more upwardly the conductive layer is located, the broader a width of the step is.

Claims

1. A three-dimensional semiconductor device, comprising:

a semiconductor substrate;

a plurality of conductive layers and insulating layers stacked alternately above the semiconductor substrate; and

a plurality of contacts extending in a stacking direction of the plurality of conductive layers and insulating layers,

the plurality of conductive layers forming a stepped portion having positions of ends of the plurality of conductive layers gradually shifted from an upper layer to a lower layer,

the plurality of contacts being connected respectively to each of steps of the stepped portion, and

the stepped portion being formed such that, at least from an uppermost conductive layer to a certain conductive layer, the more upwardly the conductive layer is located, the broader a width of the step is.

2. The three-dimensional semiconductor device according to claim 1, wherein

the stepped portion is formed such that, regarding conductive layers in layers lower than the certain conductive layer, the more downwardly the conductive layer is located, the broader the width of the step is.

3. The three-dimensional semiconductor device according to claim 1, wherein

the steps of the stepped portion are arranged in a matrix in a first direction parallel to a main surface of the semiconductor substrate and a second direction parallel to the main surface of the semiconductor substrate and orthogonal to the first direction.

4. The three-dimensional semiconductor device according to claim 2, wherein

the steps of the stepped portion are arranged in a matrix in a first direction parallel to a main surface of the semiconductor substrate and a second direction parallel to the main surface of the semiconductor substrate and orthogonal to the first direction.

5. The three-dimensional semiconductor device according to claim 1, wherein

the contacts are formed in a tapered shape.

6. The three-dimensional semiconductor device according to claim 1, further comprising:

a memory cell array including a plurality of memory cells arranged three-dimensionally on the semiconductor substrate,

wherein the conductive layers are connected to the memory cell array.

7. A nonvolatile semiconductor memory device, comprising:

a semiconductor substrate; and

a memory string provided on the semiconductor substrate and including a plurality of memory cells connected in series,

the memory string comprising;

a semiconductor layer extending in a perpendicular direction to a main surface of the semiconductor substrate and functioning as a body of the memory cells;

a charge storage layer provided on a side surface of the semiconductor layer and configured to store a charge;

a plurality of conductive layers extending in the perpendicular direction to the main surface of the semiconductor substrate via insulating layers, each of the conductive layers sandwiching the charge storage layer between the conductive layer and the semiconductor layer and functioning as a gate of the memory cells; and

a plurality of contacts extending in the perpendicular direction to the main surface of the semiconductor substrate and connected to ends of the conductive layers,

the plurality of conductive layers including a stepped portion having positions of ends of the plurality of conductive layers gradually shifted from an upper layer to a lower layer,

the plurality of contacts being connected respectively to each of steps of the stepped portion, and

the stepped portion being formed such that, at least from an uppermost conductive layer to a certain conductive layer, the more upwardly the conductive layer is located, the broader a width of the step is.

8. The nonvolatile semiconductor memory device according to claim 7, wherein

the stepped portion is formed such that, regarding conductive layers in layers lower than the certain conductive layer, the more downwardly the conductive layer is located, the broader the width of the step is.

9. The nonvolatile semiconductor memory device according to claim 7, wherein

the steps of the stepped portion are arranged in a matrix in a first direction parallel to the main surface of the semiconductor substrate and a second direction parallel to the main surface of the semiconductor substrate and orthogonal to the first direction.

10. The nonvolatile semiconductor memory device according to claim 8, wherein

the steps of the stepped portion are arranged in a matrix in a first direction parallel to the main surface of the semiconductor substrate and a second direction parallel to the main surface of the semiconductor substrate and orthogonal to the first direction.

11. The nonvolatile semiconductor memory device according to claim 7, wherein

the contacts are formed in a tapered shape.

12. The nonvolatile semiconductor memory device according to claim 8, wherein

the contacts are formed in a tapered shape.

13. The nonvolatile semiconductor memory device according to claim 7, wherein

the semiconductor layer comprises:

a pair of columnar semiconductor layers extending in the perpendicular direction to the main surface of the semiconductor substrate; and

a joining semiconductor layer configured to join lower ends of the pair of columnar semiconductor layers.

14. A method of manufacturing a three-dimensional semiconductor device, comprising:

stacking a plurality of conductive layers and insulating layers alternately on a semiconductor substrate;

forming a resist on a stacked body of the conductive layers and the insulating layers;

executing sequentially a selective etching of the conductive layers and the insulating layers by the resist while reducing the resist, thereby forming a stepped portion having positions of ends of the plurality of conductive layers gradually shifted from an upper layer to a lower layer; and

connecting contacts respectively to each of steps of the stepped portion, the contacts extending in a stacking direction,

formation of the stepped portion being executed while adjusting a reduction width of the resist such that, at least from an uppermost layer to a certain conductive layer, the more upwardly the conductive layer is located, the broader a width of the step is.

15. The method of manufacturing a three-dimensional semiconductor device according to claim 14, wherein

formation of the stepped portion comprises:

at least from the uppermost layer to the certain conductive layer, executing sequentially a selective etching of the conductive layers and the insulating layers by the resist while reducing the resist, thereby forming the stepped portion having positions of ends of the plurality of conductive layers gradually shifted from an upper layer to a lower layer; and

,

regarding from the certain conductive layer to a lowermost conductive layer, executing sequentially a selective etching of the conductive layers and the insulating layers by the resist while performing an additional application of the resist to increase a range of the resist, thereby forming the stepped portion having positions of ends of the plurality of conductive layers gradually shifted from an upper layer to a lower layer.

16. The method of manufacturing a three-dimensional semiconductor device according to claim 14, wherein

formation of the stepped portion comprises:

forming a one-dimensional stepped portion having positions of ends of the plurality of conductive layers gradually shifted in a first direction from an upper layer to a lower layer; and

,

after forming the one-dimensional stepped portion, forming a two-dimensional stepped portion having the one-dimensional stepped portion gradually shifted in a second direction orthogonal to the first direction from an upper layer to a lower layer.

17. The method of manufacturing a three-dimensional semiconductor device according to claim 15, wherein

formation of the stepped portion comprises:

forming a one-dimensional stepped portion having positions of ends of the plurality of conductive layers gradually shifted in a first direction from an upper layer to a lower layer; and

,

after forming the one-dimensional stepped portion, forming a two-dimensional stepped portion having the one-dimensional stepped portion gradually shifted in a second direction orthogonal to the first direction from an upper layer to a lower layer.

18. The method of manufacturing a three-dimensional semiconductor device according to claim 14, wherein

formation of the stepped portion comprises

increasing the reduction width of the resist by 10% or more over the reduction width of the resist in an immediately prior process.

19. The method of manufacturing a three-dimensional semiconductor device according to claim 15, wherein

formation of the stepped portion comprises

increasing the reduction width of the resist by 10% or more over the reduction width of the resist in an immediately prior process.

20. The method of manufacturing a three-dimensional semiconductor device according to claim 14, further comprising:

forming a contact on each of the steps of the stepped portions, the contact having a tapered shape and extending in the stacking direction.