FIELD EFFECT TRANSISTOR AND SCHOTTKY DIODE STRUCTURES

• US 20120319197A1
• Filed: 08/30/2012
• Published: 12/20/2012
• Est. Priority Date: 04/06/2005
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Kocon, Christopher Boguslaw, Sapp, Steven, Thorup, Paul, Probst, Dean, Herrick, Robert, Losee, Becky, Yilmaz, Hamza, Rexer, Christopher Lawrence, Calafut, Daniel
• Granted Patent: US 8,680,611 B2
• Time in Patent Office: Days
• US Class Current: 257/331
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

In accordance with an embodiment a structure can include a monolithically integrated trench field-effect transistor (FET) and Schottky diode. The structure can include a first gate trench extending into a semiconductor region, a second gate trench extending into the semiconductor region, and a source region flanking a side of the first gate trench. The source region can have a substantially triangular shape, and a contact opening extending into the semiconductor region between the first gate trench and the second gate trench. The structure can include a conductor layer disposed in the contact opening to electrically contact the source region along at least a portion of a slanted sidewall of the source region, and the semiconductor region along a bottom portion of the contact opening. The conductor layer can form a Schottky contact with the semiconductor region.

Claims

1. A structure comprising a monolithically integrated trench field-effect transistor (FET) and Schottky diode, the structure further comprising:

a first gate trench extending into a semiconductor region;

a second gate trench extending into the semiconductor region;

a source region flanking a side of the first gate trench, the source region having a substantially triangular shape;

a contact opening extending into the semiconductor region between the first gate trench and the second gate trench; and

a conductor layer disposed in the contact opening to electrically contact the source region along at least a portion of a slanted sidewall of the source region, and the semiconductor region along a bottom portion of the contact opening, the conductor layer forming a Schottky contact with the semiconductor region.

2. The structure of claim 1, wherein at least one of the semiconductor region or the source region includes at least one of one of silicon, silicon carbide, gallium nitride, and gallium arsenide.

3. The structure of claim 1, wherein the semiconductor region and the source region are of a first conductivity type, the semiconductor region includes a first silicon region having a lower doping concentration than the source region, the contact opening extends into the first silicon region such that the conductor layer forms a Schottky contact with the first silicon region.

4. The structure of claim 3, wherein the trench FET is an accumulation field effect transistor, and the first silicon region is an epitaxial layer extending between the source region and a substrate of the first conductivity type, the epitaxial layer has a lower doping concentration than the substrate.

5. The structure of claim 1, wherein the first gate trench includes:

a dielectric disposed on a bottom portion of the gate trench;

a gate dielectric lining a sidewall of the gate trench, the dielectric is thicker than the gate dielectric; and

a recessed gate disposed over the dielectric.

6. The structure of claim 1, wherein the first gate trench includes:

a shield electrode in a bottom portion of the gate trench, the shield electrode is insulated from the semiconductor region by a shield dielectric layer; and

a recessed gate disposed over the shield electrode, the recessed gate and the shield electrode have a dielectric layer disposed therebetween.

7. A structure comprising a monolithically integrated trench field-effect transistor (FET) and Schottky diode, the structure further comprising:

a gate trench extending into a semiconductor region of a first conductivity type;

a source region of the first conductivity type disposed on a side of the gate trench;

a shield electrode disposed in a bottom portion of the gate trench, the shield electrode being insulated from the semiconductor region by a shield dielectric layer;

a gate disposed over the shield electrode in the gate trench, the gate electrode and the shield electrode having a inter-electrode dielectric layer therebetween;

a dielectric cap over the gate; and

a conductor layer contacting the source region and the semiconductor region such that the conductor layer forms a Schottky contact with the semiconductor region.

8. The structure of claim 7, wherein at least one of the semiconductor region or the source region includes at least one of silicon, silicon carbide, gallium nitride, and gallium arsenide.

9. The structure of claim 7, wherein the source region is a first source region, the gate trench is a first gate trench,

the structure further comprising:

a second source region disposed on a side of a second gate trench; and

a contact opening extending into the semiconductor region between the first source region and the second source region, the conductor layer contacting the semiconductor region through the contact opening.

10. The structure of claim 7, wherein the source region is a first source region, the gate trench is a first gate trench,

the structure further comprising:

a second source region disposed on a side of a second gate trench, the semiconductor region is an epitaxial layer extending between the first source region, the second source region, and a substrate of the first conductivity type, the epitaxial layer having a lower doping concentration than the substrate and the source region.

11-31. -31. (canceled)

32. A structure comprising a monolithically integrated trench field-effect transistor (FET) and Schottky diode, the structure further comprising:

a gate trench extending into a semiconductor region of a first conductivity type, the gate trench having a recessed gate therein with a dielectric material disposed on the recessed gate;

a source region of the first conductivity type disposed on a side of the gate trench, the source region having an upper surface recessed relative to an upper surface of the dielectric material disposed on the recessed gate;

a body region of a second conductivity type extending along a sidewall of the gate trench between the source region and the semiconductor region;

a contact opening extending into the semiconductor region; and

a conductor layer disposed in the contact opening and electrically contacting the source region, the body region, and the semiconductor region, the conductor layer forming a Schottky contact with at least a portion of the semiconductor region.

33. The structure of claim 32, wherein the contact opening extends to a depth below a bottom surface of the body region.

34. The structure of claim 32, further comprising:

a dielectric spacer between the source region and the conductor layer.

35. The structure of claim 32, wherein the conductor layer electrically contacts the source region along a top surface and a sidewall of the source region.

36. The structure of claim 32, further comprising:

a gate dielectric lining a sidewall of the gate trench; and

a thick bottom dielectric disposed in a bottom portion of the gate trench below the recessed gate, the thick bottom dielectric being thicker than the gate dielectric.

37. The structure of claim 32, further comprising:

a shield electrode disposed below the recessed gate, the recessed gate and the shield electrode having a inter-electrode dielectric layer therebetween; and

a shield dielectric insulating the shield electrode from the semiconductor region.

38. A structure comprising a monolithically integrated trench FET and Schottky diode, the structure further comprising:

an epitaxial layer disposed on a substrate;

a gate trench extending into and terminating within the epitaxial layer, the gate trench having a recessed gate disposed therein and a dielectric material disposed on the recessed gate;

a source region disposed on a side of the gate trench;

a contact opening extending into the epitaxial layer; and

a conductor layer disposed in the contact opening and electrically contacting the source region and the epitaxial layer, the conductor layer forming a Schottky contact with the epitaxial layer.

39. The structure of claim 38, wherein the epitaxial layer and the source region include at least one of silicon carbide, gallium nitride, and gallium arsenide.

40. The structure of claim 38, wherein the source region has a top surface below a top surface of the dielectric material.

41. The structure of claim 38, wherein the contact opening extends into the epitaxial layer to a depth greater than one half a depth of the gate trench.

42. The structure of claim 38, further comprising a dielectric spacer between the source region and the conductor layer.

43. The structure of claim 38, wherein the conductor layer electrically contacts the source region along a top surface and a sidewall of the source region.

44. The structure of claim 38, further comprising:

a gate dielectric lining a sidewall of the gate trench; and

a thick bottom dielectric disposed on a bottom portion of the gate trench and disposed below the recessed gate, the thick bottom dielectric having a thickness greater than a thickness of the gate dielectric.

45. The structure of claim 38, further comprising:

a shield electrode disposed below the recessed gate, the recessed gate and the shield electrode having an inter-electrode dielectric layer therebetween; and

a shield dielectric insulating the shield electrode from the epitaxial layer.

46. A structure, comprising:

a gate trench extending into a semiconductor region, the gate trench having a gate disposed therein with a dielectric material disposed on the gate;

a semiconductor source spacer disposed on a side of the gate trench such that the semiconductor source spacer located between the gate trench forming at least a portion of a contact opening; and

a conductor layer disposed in the contact opening and contacting the semiconductor source spacer and the semiconductor region, the conductor layer forming a Schottky contact with the semiconductor region.

47. The structure of claim 46, wherein the contact opening extends into the semiconductor region such that the Schottky contact is formed below the semiconductor source spacer.

48. The structure of claim 46, further comprising:

a region in contact with the conductor layer through the contact opening, the region have a conductivity type opposite to a conductivity type of the semiconductor region.

49. The structure of claim 46, wherein the semiconductor source spacer includes at least one of polysilicon and polysilicon carbide, the semiconductor region includes at least one of silicon, silicon carbide, gallium nitride, and gallium arsenide.

50. The structure of claim 46, wherein the gate trench is associated with an accumulation field effect transistor, and the semiconductor region is an epitaxial layer extending between the semiconductor source spacer and a substrate,

the epitaxial layer, the semiconductor source spacer, and the substrate are of the same conductivity type, the epitaxial layer has a lower doping concentration than the substrate.

51. The structure of claim 46, further comprising:

a thick bottom dielectric disposed below the gate in a bottom portion of the gate trench; and

a gate dielectric lining a sidewall of the gate trench, the thick bottom dielectric having a thickness greater than a thickness of the gate dielectric.

52. The structure of claim 46, wherein the gate is a recessed gate,

the structure further comprising:

a shield electrode disposed below the recessed gate within a bottom portion of the gate trench, the shield electrode being insulated from the recessed gate by a dielectric layer and being insulated from the semiconductor region by a shield dielectric layer.