Trench Gated Power Device With Multiple Trench Width and its Fabrication Process

• US 20120319199A1
• Filed: 06/18/2012
• Published: 12/20/2012
• Est. Priority Date: 06/20/2011
• Status: Active Grant

• Current Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Zeng, Jun, Darwish, Mohamed N.
• Granted Patent: US 8,680,607 B2
• Time in Patent Office: Days
• US Class Current: 257/334
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Power devices, and related process, where both gate and field plate trenches have multiple stepped widths, using self-aligned process steps.

Claims

1. A semiconductor device, comprising:

a semiconductor mass;

gate electrodes in first trenches in said semiconductor mass, and field plate electrodes in second trenches in said semiconductor mass;

wherein said first trenches and said second trenches have substantially the same depth;

wherein said first and said second trenches each have a top portion which is wider than a middle portion thereof which has substantially vertical sidewalls, and also a bottom portion which is narrower than said middle portion;

a first-conductivity-type source region, in said semiconductor mass, near said first trenches, and a second-conductivity-type body region adjacent said first trenches, and a second-conductivity-type body contact region surrounding said second trenches.

2. The semiconductor device of claim 1, wherein said first conductivity type is n-type, and said second conductivity type is p-type.

3. The semiconductor device of claim 1, wherein said semiconductor mass consists essentially of silicon.

4. The semiconductor device of claim 1, wherein said gate electrodes are made of doped polysilicon.

5. The semiconductor device of claim 1, wherein said middle portion of each said trench has a greater vertical extent than said bottom portion thereof, and said bottom portion of each said trench has a greater vertical extent than said top portion thereof.

6. The semiconductor device of claim 1, wherein said gate electrode does not extend into said bottom portion of said first trench, and said field plate electrode does extend into said bottom portion of said second trench.

7. The semiconductor device of claim 1, wherein doping for said body region is provided by a well diffusion process.

8. A semiconductor device, comprising:

a semiconductor mass;

gate electrodes in first trenches in said semiconductor mass, and field plate electrodes in second trenches in said semiconductor mass;

wherein said first trenches and said second trenches both extend into a first surface of said semiconductor mass, and all have substantially the same depth;

wherein said first and said second trenches each have a top portion which is wider than a middle portion thereof which has substantially vertical sidewalls, and also a bottom portion which is narrower than said middle portion;

and wherein said gate electrodes, but not said field plate electrodes, are connected directly to receive a gate drive waveform;

a first-conductivity-type source region, in said semiconductor mass, near said first trenches, and a second-conductivity-type body region adjacent said first trenches, and a second-conductivity-type body contact region surrounding and self-aligned to said second trenches; and

a first-conductivity-type drain region at a second surface of said semiconductor mass;

whereby, in the ON state, voltage applied to said gate electrode controls majority carrier emission from said source, to thereby allow current conduction between said source and said drain; and

whereby said field plate electrodes affect isopotential contours, in the OFF state, to increase the breakdown voltage between said source and said drain.

9. The semiconductor device of claim 8, wherein said first conductivity type is n-type, and said second conductivity type is p-type.

10. The semiconductor device of claim 8, wherein said semiconductor mass consists essentially of silicon.

11. The semiconductor device of claim 8, wherein said gate electrodes are made of doped polysilicon.

12. The semiconductor device of claim 8, wherein said middle portion of each said trench has a greater vertical extent than said bottom portion thereof, and said bottom portion of each said trench has a greater vertical extent than said top portion thereof.

13. The semiconductor device of claim 8, wherein said gate electrode does not extend into said bottom portion of said first trench, and said field plate electrode does extend into said bottom portion of said second trench.

14. The semiconductor device of claim 8, wherein doping for said body region is provided by a well diffusion process.

15. A semiconductor device, comprising:

a semiconductor mass;

gate electrodes in first trenches in said semiconductor mass, and field plate electrodes in second trenches in said semiconductor mass;

wherein said first trenches and said second trenches have substantially the same depth;

wherein said first and said second trenches each have a top portion which is wider than a middle portion thereof which has substantially vertical sidewalls, and also a bottom portion which is narrower than said middle portion;

a first-conductivity-type source region, in said semiconductor mass, adjacent and self-aligned to said first trenches;

a second-conductivity-type body region adjacent said first trenches;

a second-conductivity-type body contact region surrounding and self-aligned to said second trenches; and

modified regions, below and self-aligned to said second trenches, which have a smaller net concentration of second-conductivity-type dopants than said body region does.

16. The semiconductor device of claim 15, wherein said modified regions are near-intrinsic.

17. The semiconductor device of claim 15, wherein said modified regions have the same conductivity type as said body region.

18. The semiconductor device of claim 15, wherein said first conductivity type is n-type, and said second conductivity type is p-type.

19. The semiconductor device of claim 15, wherein said semiconductor mass consists essentially of silicon.

20. The semiconductor device of claim 15, wherein said gate electrodes are made of doped polysilicon.

21-43. -43. (canceled)