INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LASER HOLE AND METHOD OF MANUFACTURE THEREOF

• US 20120319294A1
• Filed: 06/17/2011
• Published: 12/20/2012
• Est. Priority Date: 06/17/2011
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Lte.
• Original Assignee: Stats Chippac BVI limited (JCET Group Co., Ltd.)
• Inventors: Lee, HyungMin, Chi, HeeJo, Park, YeongIm
• Granted Patent: US 8,710,668 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48235 connecting the wire to a via metallisation of the item
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06558 the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3135 Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/03 : all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A method of manufacture of an integrated circuit packaging system includes: providing a substrate; molding a first encapsulation above the substrate; forming a via through the first encapsulation; mounting an integrated circuit above the substrate and between sides of the first encapsulation; and forming a second encapsulation covering the integrated circuit and the first encapsulation.

Claims

1. A method of manufacture of an integrated circuit packaging system comprising:

providing a substrate;

molding a first encapsulation above the substrate;

forming a via through the first encapsulation;

mounting an integrated circuit above the substrate and between sides of the first encapsulation; and

forming a second encapsulation covering the integrated circuit and the first encapsulation.

2. The method as claimed in claim 1 further comprising connecting a second integrated circuit above the first integrated circuit and directly connected to the via with an interconnect.

3. The method as claimed in claim 1 further comprising connecting an external package to the substrate through the via.

4. The method as claimed in claim 1 wherein encapsulating the integrated circuit includes forming an exterior surface coplanar with the first encapsulation and coplanar with the substrate.

5. The method as claimed in claim 1 wherein forming the via includes forming the via coplanar with a planar surface of the first encapsulation.

6. A method of manufacture of an integrated circuit packaging system comprising:

providing a substrate;

molding a first encapsulation above the substrate and along a perimeter region of the substrate;

forming a first via through the first encapsulation;

mounting an integrated circuit between sides of the first encapsulation above the substrate and directly connected to the substrate with an interconnect;

forming a second encapsulation covering the integrated circuit and the first encapsulation; and

forming a second via through the second encapsulation from the first via and exposed from a top surface of the second encapsulation.

7. The method as claimed in claim 6 wherein forming the first via includes forming the first via having a pillar, a paste, and a spheroid.

8. The method as claimed in claim 6 wherein forming the first via includes forming the first via having a vertical conductor.

9. The method as claimed in claim 6 wherein encapsulating the integrated circuit includes forming the top surface having a depression.

10. The method as claimed in claim 6 wherein forming the second via includes forming the second via coplanar with the top surface of the second encapsulation.

11. An integrated circuit packaging system comprising:

a substrate;

a first encapsulation molded above the substrate;

a via formed through the first encapsulation;

an integrated circuit mounted above the substrate and between sides of the first encapsulation; and

a second encapsulation encapsulating covering the integrated circuit and the first encapsulation.

12. The system as claimed in claim 11 further comprising a second integrated circuit mounted above the first integrated circuit and directly connected to the via with an interconnect.

13. The system as claimed in claim 11 further comprising an external package connected to the substrate through the via.

14. The system as claimed in claim 11 further comprising an exterior surface of the second encapsulation coplanar with the first encapsulation and coplanar with the substrate.

15. The system as claimed in claim 11 wherein the via is formed coplanar with a planar surface of the first encapsulation.

16. The system as claimed in claim 11 wherein:

the via is a first via;

the first encapsulation is formed along a perimeter region of the substrate;

the integrated circuit is directly connected to the substrate with an interconnect; and

further comprising;

a second via formed through the second encapsulation from the first via and exposed from a top surface of the second encapsulation.

17. The system as claimed in claim 16 wherein the first via has a pillar, a paste, and a spheroid.

18. The system as claimed in claim 16 wherein the first via has a vertical conductor.

19. The system as claimed in claim 16 wherein the top surface has a depression.

20. The system as claimed in claim 16 wherein the second via is formed coplanar with the top surface of the second encapsulation.