DC TO DC CONVERTER WITH RIPPLE CANCELLATION

• US 20120319478A1
• Filed: 06/20/2011
• Published: 12/20/2012
• Est. Priority Date: 06/20/2011
• Status: Abandoned Application

• Current Assignee: Volterra Semiconductor Corporation (Analog Devices, Inc.)
• Original Assignee: Volterra Semiconductor Corporation (Analog Devices, Inc.)
• Inventors: Gentchev, Angel, Ikriannikov, Alexander, Stratakos, Anthony
• Application Number:
  US13/164,388
• Publication Number:
  US 20120319478A1
• Time in Patent Office: Days
• US Class Current: 307/28
• CPC Class Codes: H02J 1/102 being switching converters H02J1/108, H02J1/12 take precedence
• CPC Class Codes: H02M 1/0064 Magnetic structures combining different functions, e.g. storage, filtering or transformation
• CPC Class Codes: H02M 1/14 Arrangements for reducing ripples from dc input or output
• CPC Class Codes: H02M 3/1586 switched with a phase shift, i.e. interleaved

Abstract

Ripple cancellation techniques are described for various DC to DC converters having multiple parallel phases with magnetically coupled inductors.

Claims

1. A DC to DC converter configured to convert a first voltage, V1, to a second voltage, V2, the DC to DC converter including a first stage and a second stage, the second stage being configured to generate V2 and including N parallel phases, each of the N parallel phases including an inductor and switching circuitry configured to define a conduction interval corresponding to a duty cycle D, the conduction intervals of the respective N parallel phases being substantially evenly distributed over 360 degrees, wherein the inductors of all of the N parallel phases are magnetically coupled to each other, wherein D is about M/N, and wherein M is an integer, 0<

M<

N.

2. The DC to DC converter of claim 1, wherein the first stage includes K parallel phases, each of the K parallel phases including an inductor and switching circuitry configured to define a conduction interval, the conduction intervals of the respective K parallel phases being substantially evenly distributed over 360 degrees, wherein the inductors of all of the N parallel phases are magnetically coupled to each other.

3. The DC to DC converter of claim 2, wherein each of the conduction intervals of the K parallel phases corresponds to a duty cycle D2, wherein D2 is about L/K, and wherein L is an integer, 0<

L<

K.

4. The DC to DC converter of claim 3, further comprising a single controller configured to control the duty cycles of the N parallel phases and the duty cycles of the K parallel phases.

5. The DC to DC converter of claim 1, wherein each of the stages employs one of a Buck topology, a boost topology, a Buck-boost topology, or an isolated topology.

6. The DC to DC converter of claim 1, wherein each inductor of each of the N parallel phases comprises a winding wound around a common core shared by all of the inductors.

7. The DC to DC converter of claim 6, wherein each winding is characterized by a leakage inductance and a magnetizing inductance, and wherein the magnetizing inductance of each winding is greater than at least about three times the leakage inductance of any of the windings.

8. The DC to DC converter of claim 1, wherein the first stage is configured to generate an intermediate voltage, Vint, for use by the second stage in generating V2, and wherein the first stage is configured to regulate the intermediate voltage Vint by sensing one or both of Vint and V2.

9. The DC to DC converter of claim 1, wherein the first stage is configured to generate an intermediate voltage, Vint, for use by the second stage in generating V2, and wherein the first stage is configured to generate the intermediate voltage Vint using an open-loop control mechanism.

10. The DC to DC converter of claim 9, wherein the first stage is configured to operate in accordance with one or more duty cycles, and wherein the open-loop control mechanism selects the one or more duty cycles.

11. The DC to DC converter of claim 1, wherein the first stage is configured to generate an intermediate voltage, Vint, for use by the second stage in generating V2, wherein the first and second stages are configured to independently regulate Vint and V2, respectively, and wherein a control loop of the second stage has a bandwidth higher than a bandwidth of a control loop of the first stage.

12. The DC to DC converter of claim 1, further comprising open-loop control circuitry configured to maintain the duty cycles of the N parallel phases.

13. The DC to DC converter of claim 1, further comprising closed-loop control circuitry configured to maintain V2 with reference to one or more operational parameters of the N parallel phases.

14. The DC to DC converter of claim 13, wherein the one or more operational parameters comprises a current associated with each of the N parallel phases.

15. The DC to DC converter of claim 14, wherein the closed-loop control circuitry is configured to compute an average of the currents and to force each of the currents toward the average.

16. The DC to DC converter of claim 14, wherein the closed-loop control circuitry is configured to sense the current associated with each of the phases and to switch a first one of the N parallel phases in response to the corresponding current crossing a threshold defined with reference to V2.

17. The DC to DC converter of claim 16, wherein the threshold comprises one or either of a high current threshold or a low current threshold.

18. The DC to DC converter of claim 14, wherein the closed-loop control circuitry is configured to sense the current associated with each of the phases and to switch a first one of the N parallel phases on in response to the corresponding current being a lowest one of the currents of all of the phases.

19. A DC to DC converter configured to convert a first voltage, V1, to a second voltage, V2, the DC to DC converter comprising N parallel phases configured to receive V1 and generate V2, each of the N parallel phases including an inductor and switching circuitry configured to define a conduction interval corresponding to a duty cycle D, the conduction intervals of the respective N parallel phases being substantially evenly distributed over 360 degrees, wherein the inductors of all of the N parallel phases are magnetically coupled to each other, wherein D is about M/N, and wherein M is an integer, 0<

M<

N.

20. The DC to DC converter of claim 19, wherein the DC to DC converter employs one of a Buck topology, a boost topology, a Buck-boost topology, or an isolated topology.

21. The DC to DC converter of claim 19, wherein each inductor of each of the N parallel phases comprises a winding wound around a common core shared by all of the inductors.

22. The DC to DC converter of claim 21, wherein each winding is characterized by a leakage inductance and a magnetizing inductance, and wherein the magnetizing inductance of each winding is greater than at least about three times the leakage inductance of any of the windings.

23. The DC to DC converter of claim 19, further comprising open-loop control circuitry configured to maintain the duty cycles of the N parallel phases.

24. The DC to DC converter of claim 19, further comprising closed-loop control circuitry configured to maintain V2 with reference to one or more operational parameters of the N parallel phases.

25. The DC to DC converter of claim 24, wherein the one or more operational parameters comprises a current associated with each of the N parallel phases.

26. The DC to DC converter of claim 25, wherein the closed-loop control circuitry is further configured to compute an average of the currents and to force each of the currents toward the average.

27. The DC to DC converter of claim 25, wherein the closed-loop control circuitry is configured sense the current associated with each of the phases and to switch a first one of the N parallel phases in response to the corresponding current crossing a threshold defined with reference to V2.

28. The DC to DC converter of claim 27, wherein the threshold comprises one or either of a high current threshold or a low current threshold.

29. The DC to DC converter of claim 25, wherein the closed-loop control circuitry is configured to sense the current associated with each of the phases and to switch a first one of the N parallel phases on in response to the corresponding current being a lowest one of the currents of all of the phases.

30. The DC to DC converter of claim 19 wherein the N parallel phases are included in one of a plurality of stages of the DC to DC converter, and wherein the stage of the DC to DC converter including the N parallel phases comprises one of an input stage, an intermediate stage, or an output stage of the DC to DC converter.

31. An electronic system comprising a plurality of DC to DC converters configured to generate a plurality of different DC voltages for use by a plurality of loads, a first one of the DC to DC converters comprising N parallel phases configured to receive an input voltage, V1, and generate an intermediate voltage, Vint, each of the N parallel phases including an inductor and switching circuitry configured to define a conduction interval corresponding to a duty cycle D, the conduction intervals of the respective N parallel phases being substantially evenly distributed over 360 degrees, wherein the inductors of all of the N parallel phases are magnetically coupled to each other, wherein D is about M/N, wherein M is an integer, 0<

M<

N, the electronic system further comprising a bus for distributing Vint to others of the DC to DC converters for generation of at least some of the plurality of different DC voltages.

32. The electronic system of claim 31, wherein a second one of the DC to DC converters is configured to receive Vint via the bus and includes K parallel phases, each of the K parallel phases including an inductor and switching circuitry configured to define a conduction interval corresponding to a duty cycle D2, the conduction intervals of the respective K parallel phases being substantially evenly distributed over 360 degrees, wherein the inductors of all of the K parallel phases are magnetically coupled to each other, wherein D2 is about L/K, and wherein L is an integer, 0<

L<

K.

33. The electronic system of claim 31, wherein Vint is one of the different DC voltages employed by a subset of the plurality of loads.

34. The electronic system of claim 31, wherein the plurality of different DC voltages include two or more of 1.8V, 2.5V, 3.3V, or 5V.

35. The electronic system of claim 34, wherein at least one of the two or more of 1.8V, 2.5V, 3.3V, or 5V provides a gate-drive supply voltage for one or more of the DC to DC converters.

36. The electronic system of claim 34, wherein Vint is one of the 1.8V, 2.5V, 3.3V, or 5V.

37. The electronic system of claim 34, wherein at least one of the two or more of 1.8V, 2.5V, 3.3V, or 5V provides a voltage supply for a controller associated with one or more of the DC to DC converters.

38. The electronic system of claim 31, wherein the switching circuitry for each of the N parallel phases comprises a power switch and a driver configured to drive the power switch, and wherein V1 supplies power to the driver.

39. The electronic system of claim 38, wherein the switching circuitry further comprises a controller configured to provide a drive signal to the driver, and wherein V1 supplies power to the controller.

40. The electronic system of claim 31, wherein each of the DC to DC converters employs one of a Buck topology, a boost topology, a Buck-boost topology, or an isolated topology.

41. The electronic system of claim 31, wherein each inductor of each of the N parallel phases comprises a winding wound around a common core shared by all of the inductors.

42. The electronic system of claim 41, wherein each winding is characterized by a leakage inductance and a magnetizing inductance, and wherein the magnetizing inductance of each winding is greater than at least about three times the leakage inductance of any of the windings.

43. The electronic system of claim 31, further comprising open-loop control circuitry configured to maintain the duty cycles of the N parallel phases.

44. The electronic system of claim 31, further comprising closed-loop control circuitry configured to maintain Vint with reference to one or more operational parameters of the N parallel phases.

45. The electronic system of claim 44, wherein the one or more operational parameters comprises a current associated with each of the N parallel phases.

46. The electronic system of claim 45, wherein the closed-loop control circuitry is configured to compute an average of the currents and to force each of the currents toward the average.

47. The electronic system of claim 45, wherein the closed-loop control circuitry is configured sense the current associated with each of the phases and to switch a first one of the N parallel phases in response to the corresponding current crossing a threshold defined with reference to Vint.

48. The electronic system of claim 47, wherein the threshold comprises one or either of a high current threshold or a low current threshold.

49. The electronic system of claim 45, wherein the closed-loop control circuitry is configured to sense the current associated with each of the phases and to switch a first one of the N parallel phases on in response to the corresponding current being a lowest one of the currents of all of the phases.

50. An electronic system comprising a plurality of DC to DC converters configured to generate a plurality of different DC voltages for use by a plurality of loads, a particular one of the DC to DC converters having N parallel phases configured to receive a distribution voltage, Vdist, and generate an output voltage, Vout, for use by a corresponding one of the loads, each of the N parallel phases including an inductor and switching circuitry configured to define a conduction interval corresponding to a duty cycle D, the conduction intervals of the respective N parallel phases being substantially evenly distributed over 360 degrees, wherein the inductors of all of the N parallel phases are magnetically coupled to each other, wherein D is about M/N, and wherein M is an integer, 0<

M<

N, the electronic system further comprising a bus for distributing Vdist to others of the DC to DC converters for generation of at least some of the plurality of different DC voltages.

51. The electronic system of claim 50, wherein Vdist is selected with reference to Vout, and wherein Vout is time-varying, Vdist scaling with Vout to maintain Vout at about (M/N)*Vdist.

52. The electronic system of claim 50, wherein Vout changes in response to a command from the corresponding load, and wherein Vdist scales with Vout to maintain Vout at about (M/N)*Vdist.

53. The electronic system of claim 50, wherein each of the DC to DC converters employs one of a Buck topology, a boost topology, a Buck-boost topology, or an isolated topology.

54. The electronic system of claim 50, wherein each inductor of each of the N parallel phases comprises a winding wound around a common core shared by all of the inductors.

55. The electronic system of claim 54, wherein each winding is characterized by a leakage inductance and a magnetizing inductance, and wherein the magnetizing inductance of each winding is greater than at least about three times the leakage inductance of any of the windings.

56. The electronic system of claim 50, further comprising open-loop control circuitry configured to maintain the duty cycles of the N parallel phases.

57. The electronic system of claim 50, further comprising closed-loop control circuitry configured to maintain Vout with reference to one or more operational parameters of the N parallel phases.

58. The electronic system of claim 57, wherein the one or more operational parameters comprises a current associated with each of the N parallel phases.

59. The electronic system of claim 58, wherein the closed-loop control circuitry is configured to compute an average of the currents and to force each of the currents toward the average.

60. The electronic system of claim 58, wherein the closed-loop control circuitry is configured sense the current associated with each of the phases and to switch a first one of the N parallel phases in response to the corresponding current crossing a threshold defined with reference to Vout.

61. The electronic system of claim 60, wherein the threshold comprises one or either of a high current threshold or a low current threshold.

62. The electronic system of claim 58, wherein the closed-loop control circuitry is configured to sense the current associated with each of the phases and to switch a first one of the N parallel phases on in response to the corresponding current being a lowest one of the currents of all of the phases.

63. The electronic system of claim 50, wherein Vdist is selected with reference to Vout, and wherein Vout is adjustable, Vdist scaling with Vout to maintain Vout at about (M/N)*Vdist.

64. A DC to DC converter configured to convert a first voltage, V1, to a second voltage, V2, the DC to DC converter comprising N parallel phases configured to receive V1 and generate V2, each of the N parallel phases including an inductor and switching circuitry configured to define a conduction interval corresponding to a duty cycle, and wherein the inductors of all of the N parallel phases are magnetically coupled to each other, the DC to DC converter further comprising closed-loop control circuitry configured to maintain V2 with reference to one or more operational parameters of the N parallel phases, and to maintain currents associated with each of the N parallel phases to be substantially equal, thereby maintaining a substantially zero ripple current condition in the switching circuitry and the output conductors of the N parallel phases.

65. The DC to DC converter of claim 64, wherein the one or more operational parameters comprises the currents associated with each of the N parallel phases.

66. The DC to DC converter of claim 65, wherein the closed-loop control circuitry is configured to compute an average of the currents and to force each of the currents toward the average.

67. The DC to DC converter of claim 65, wherein the closed-loop control circuitry is configured to sense the current associated with each of the phases and to switch a first one of the N parallel phases in response to the corresponding current crossing a threshold defined with reference to V2.

68. The DC to DC converter of claim 67, wherein the threshold comprises one or either of a high current threshold or a low current threshold.

69. The DC to DC converter of claim 65, wherein the closed-loop control circuitry is configured to sense the current associated with each of the phases and to switch a first one of the N parallel phases on in response to the corresponding current being a lowest one of the currents of all of the phases.

70. The DC to DC converter of claim 64, wherein the DC to DC converter employs one of a Buck topology, a boost topology, a Buck-boost topology, or an isolated topology.

71. The DC to DC converter of claim 64, wherein each inductor of each of the N parallel phases comprises a winding wound around a common core shared by all of the inductors.

72. The DC to DC converter of claim 71, wherein each winding is characterized by a leakage inductance and a magnetizing inductance, and wherein the magnetizing inductance of each winding is greater than at least about three times the leakage inductance of any of the windings.

73. A DC to DC converter configured to convert a first voltage, V1, to a second voltage, V2, the DC to DC converter comprising N parallel phases configured to receive V1 and generate V2, each of the N parallel phases including an inductor and switching circuitry, the inductors of all of the N parallel phases being magnetically coupled to each other, the DC to DC converter further comprising closed-loop control circuitry configured to maintain currents associated with each of the N parallel phases to be substantially equal by sensing the current associated with each of the phases and switching a first one of the N parallel phases in response to the corresponding current crossing a threshold.

74. A DC to DC converter configured to convert a first voltage, V1, to a second voltage, V2, the DC to DC converter comprising N parallel phases configured to receive V1 and generate V2, each of the N parallel phases including an inductor and switching circuitry, the inductors of all of the N parallel phases being magnetically coupled to each other, the DC to DC converter further comprising closed-loop control circuitry configured to maintain currents associated with each of the N parallel phases to be substantially equal by computing an average of the currents and forcing each of the currents toward the average.

75. A DC to DC converter configured to convert a first voltage, V1, to a second voltage, V2, the DC to DC converter comprising N parallel phases configured to receive V1 and generate V2, each of the N parallel phases including an inductor and switching circuitry, the inductors of all of the N parallel phases being magnetically coupled to each other, the DC to DC converter further comprising closed-loop control circuitry configured to maintain currents associated with each of the N parallel phases to be substantially equal by sensing the current associated with each of the phases and switching a first one of the N parallel phases on in response to the corresponding current being a lowest one of the currents of all of the phases.