SYSTEM AND METHOD FOR REDUCING POWER CONSUMPTION IN A PHASED-LOCKED LOOP CIRCUIT

• US 20120319734A1
• Filed: 06/20/2011
• Published: 12/20/2012
• Est. Priority Date: 06/20/2011
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: KUMAR, Ajay, NAGARAJ, Krishnasawamy
• Granted Patent: US 8,536,910 B2
• Time in Patent Office: Days
• US Class Current: 327/3
• CPC Class Codes: H03D 13/00 Circuits for comparing the phase or frequency of two mutually-independent oscillations measuring phase G01R25/00; phase-discriminators with yes/no output G01R25/005
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump

Abstract

A phased-locked loop (PLL) circuit which comprises a phase-frequency detector (PFD) configured to receive a reference signal, a voltage-controlled oscillator (VCO) configured to produce a VCO signal, and a divider configured to divide the VCO signal thereby producing a feedback signal based on the feedback signal not being locked to the reference signal. Based on the feedback signal not being locked to the reference signal, the PFD is configured to compare an edge of the reference signal with an edge of the feedback signal to produce an error signal. Based on the feedback signal being locked to the reference signal, the PFD is configured to compare the edge of the reference signal to an edge of the VCO signal to produce an error signal and the divider is configured to be disabled.

Claims

1. A phased-locked loop (PLL) circuit comprising:

a phase-frequency detector (PFD) configured to receive a reference signal;

a voltage-controlled oscillator (VCO) configured to produce a VCO signal; and

a divider configured to divide the VCO signal thereby producing a feedback signal based on the feedback signal not being locked to the reference signal,

wherein, based on the feedback signal not being locked to the reference signal, the PFD is configured to compare an edge of the reference signal with an edge of the feedback signal to produce an error signal, and

wherein, based on the feedback signal being locked to the reference signal, the PFD is configured to compare the edge of the reference signal to an edge of the VCO signal to produce an error signal and the divider is configured to be disabled.

2. The PLL circuit of claim 1 wherein, based on the feedback signal being locked to the reference signal, the VCO signal is not provided to the divider.

3. The PLL circuit of claim 2 further comprising:

a frequency lock detector (FLD) configured to determine whether the frequency of the VCO signal is locked to the frequency of the reference signal.

4. The PLL circuit of claim 3 wherein the FLD is configured to be switched off after making the determination of whether the frequency of the VCO signal is locked to the frequency of the reference signal and switched back on a predetermined amount of time later and configured to determine whether the frequency of the VCO signal is locked to the frequency of the reference signal.

5. The PLL circuit of claim 3, wherein, based on the VCO signal not being locked to the reference signal, the divider is configured to be enabled and the VCO signal is provided to the divider.

6. The PLL circuit of claim 5, wherein based on the VCO signal not being locked to the reference signal, the PFD is configured to compare the edge of the reference signal with the edge of the feedback signal to produce the error signal.

7. The PLL circuit of claim 1, further comprising:

a charge pump (CP) configured to create an up signal or down signal based on a frequency difference between the reference signal and either the feedback signal or VCO signal determined by the PFD.

8. The PLL circuit of claim 7, wherein the CP is further configured to produce a negative charge based on the CP creating a down signal and a positive charge based on the CP creating an up signal.

9. The PLL circuit of claim 1, wherein the reference signal, VCO signal, and feedback signal are square waves.

10. A method comprising:

receiving, by a phase-frequency detector (PFD), a reference signal;

producing, by a voltage-controlled oscillator (VCO), a VCO signal;

dividing, by a divider, the VCO signal to produce a feedback signal based on the feedback signal not being locked to the reference signal;

comparing, by the PFD, an edge of the reference signal with an edge of the feedback signal to produce an error signal based on the feedback signal not being locked to the reference signal;

comparing, by the PFD, the edge of the reference signal to an edge of the VCO signal to produce an error signal based on the feedback signal being locked to the reference signal; and

disabling the divider based on the feedback signal being locked to the reference signal.

11. The method of claim 10, further comprising, not providing the VCO signal to the divider based on the feedback signal being locked to the reference signal.

12. The method of claim 11, further comprising, determining, by a frequency lock detector (FLD), whether the frequency of the VCO signal is locked to the frequency of the reference signal.

13. The method of claim of claim 12, further comprising:

switching off the FLD after making the determination of whether the frequency of the VCO signal is locked to the frequency of the reference signal; and

switching the FLD back on a predetermined amount of time after the FLD was switched off to determine whether the frequency of the VCO signal is locked to the frequency of the reference signal.

14. The method of claim 12, further comprising, enabling the divider and providing the VCO signal to the divider based on the VCO signal not being locked to the reference signal.

15. The method of claim 14, further comprising, comparing the edge of the reference signal with the edge of the feedback signal to produce the error signal based on the VCO signal not being locked to the reference signal.

16. A phase-frequency detector (PFD) comprising:

a delay buffer configured to receive a reference signal and produce a delayed reference signal;

a first flip flop configured to receive the delayed reference signal as its C input;

a second flip flop configured to receive a feedback signal as its C input based on the feedback signal not being locked to the reference signal and a voltage-controlled oscillator (VCO) signal as its C input based on the feedback signal being locked to the reference signal; and

a third flip flop configured to receive the reference signal as its C input.

17. The PFD of claim 16, wherein the reference signal, feedback signal, and VCO signal are square waves.

18. The PFD of claim 16, wherein the second flip flop is further configured to receive an output of the third flip flop as its D input based on the feedback signal being locked to the reference signal.

19. The PFD of claim 16, wherein an output of the first flip flop is an up signal.

20. The PFD of claim 16, wherein an output of the second flip flop is a down signal.