HIGH SPEED RESISTOR-DAC FOR SAR DAC
First Claim
1. A singled-ended, successive approximation register (SAR) analog-to-digital converter (ADC) configured to convert an analog input voltage to a digital representation comprising m upper order bits and a number of lower order bits, comprising:
- SAR logic;
a resistive network;
a plurality of switches individually controlled by said SAR logic;
a plurality of most significant bit (MSB) capacitors, some of which are connected to a static voltage; and
a pair of least significant bit (LSB) capacitors, a first LSB capacitor connected to one of the switches that selectively couples said first LSB capacitor to a reference voltage (Vref) or a selected first tap in said resistive network, and a second LSB capacitor connected to one of the switches that selectively couples said second LSB capacitor to the analog input voltage or a selected second tap in said resistive network;
wherein said plurality of switches also comprises two sets of switches coupled to said resistive network, each set of switches is configured to couple a selected tap to each of said first and second LSB capacitors; and
wherein, when determining the lower order bits, said SAR logic is configured to control the sets of switches to change the first and second taps from one cycle in which one of the lower order bits is determined to a next cycle in which the next of the lower order bits is determined so that the voltage of the first and second taps changes by Vref/[2(n−
m+1)] where n is the nth bit being determined.
1 Assignment
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Accused Products
Abstract
A singled-ended, successive approximation register analog-to-digital converter convert an analog input voltage to a digital representation comprising m upper order bits and a number of lower order bits. The SAR ADC comprises SAR logic, a resistive network, multiple switches, and first and second LSB capacitors. The switches also comprises two sets of switches coupled to the resistive network, each set of switches is configured to couple a selected tap to each of the first and second LSB capacitors. When determining the lower order bits, the SAR logic is configured to control the sets of switches to change the first and second taps from one cycle in which one of the lower order bits is determined to a next cycle in which the next of the lower order bits is determined so that the voltage of both taps changes by a decreasing amount with each succeeding bit being determined.
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Citations
14 Claims
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1. A singled-ended, successive approximation register (SAR) analog-to-digital converter (ADC) configured to convert an analog input voltage to a digital representation comprising m upper order bits and a number of lower order bits, comprising:
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SAR logic; a resistive network; a plurality of switches individually controlled by said SAR logic; a plurality of most significant bit (MSB) capacitors, some of which are connected to a static voltage; and a pair of least significant bit (LSB) capacitors, a first LSB capacitor connected to one of the switches that selectively couples said first LSB capacitor to a reference voltage (Vref) or a selected first tap in said resistive network, and a second LSB capacitor connected to one of the switches that selectively couples said second LSB capacitor to the analog input voltage or a selected second tap in said resistive network; wherein said plurality of switches also comprises two sets of switches coupled to said resistive network, each set of switches is configured to couple a selected tap to each of said first and second LSB capacitors; and wherein, when determining the lower order bits, said SAR logic is configured to control the sets of switches to change the first and second taps from one cycle in which one of the lower order bits is determined to a next cycle in which the next of the lower order bits is determined so that the voltage of the first and second taps changes by Vref/[2(n−
m+1)] where n is the nth bit being determined. - View Dependent Claims (2, 3, 4)
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5. A singled-ended, successive approximation register (SAR) analog-to-digital converter (ADC) configured to convert an analog input voltage to a digital representation comprising m upper order bits and a number of lower order bits, comprising:
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SAR logic a resistive network; a plurality of switches individually controlled by said SAR logic; and a pair of least significant bit (LSB) capacitors, a first LSB capacitor connected to one of the switches that selectively couples said first LSB capacitor to a reference voltage (Vref) or a selected first tap in said resistive network, and a second LSB capacitor connected to one of the switches that selectively couples said second LSB capacitor to the analog input voltage or a selected second tap in said resistive network; wherein said plurality of switches also comprises two sets of switches coupled to said resistive network, each set of switches is configured to couple a selected tap to each of said first and second LSB capacitors; and wherein, when determining the lower order bits, said SAR logic is configured to control the sets of switches to change the first and second taps from one cycle in which one of the lower order bits is determined to a next cycle in which the next of the lower order bits is determined so that the voltage of both the first and second taps changes by a decreasing amount with each succeeding bit being determined. - View Dependent Claims (6, 7, 8, 9, 10)
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11. A method of converting an analog input voltage to a digital representations, comprising:
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determining each of a plurality of upper order bits; for each of a plurality of lower order bits, changing a voltage to each of a pair of capacitors and comparing the analog input voltage to a node voltage generated, at least in part, by said capacitors. - View Dependent Claims (12, 13, 14)
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Specification