NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE

• US 20120320678A1
• Filed: 03/20/2012
• Published: 12/20/2012
• Est. Priority Date: 06/14/2011
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: MAEJIMA, Hiroshi, Sakaguchi, Natsuki
• Granted Patent: US 8,542,533 B2
• Time in Patent Office: Days
• US Class Current: 365/185.11
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

In performing a read operation of a memory transistor, a control circuit supplies a first voltage to a selected word line connected to a selected memory transistor. A second voltage is supplied to a non-selected word line connected to a non-selected memory transistor other than the selected memory transistor, the second voltage being higher than the first voltage. A third voltage is supplied to a bit line. A fourth voltage lower than the third voltage is supplied to, among source lines, a selected source line connected to a memory string including the selected memory transistor in a selected memory block. A fifth voltage substantially the same as the third voltage is supplied to, among the source lines, a non-selected source line connected to a non-selected memory string in the selected memory block.

Claims

1. A non-volatile semiconductor memory device comprising:

a memory cell array comprising a plurality of memory blocks;

a plurality of memory strings formed in each of the memory blocks, each memory string including a plurality of memory transistors connected in series, the plurality of memory transistors stacked in a direction perpendicular to a semiconductor substrate;

a drain-side select transistor having a first end connected to a first end portion of each of the memory strings;

a source-side select transistor having a first end connected to a second end portion of each of the memory strings;

a plurality of word lines, each word line being commonly connected to the memory strings disposed in each of the memory blocks;

a plurality of bit lines, each bit line being connected to second ends of the drain-side select transistors in respective memory blocks;

a plurality of source lines provided in each of the memory blocks, each of the source lines being connected to a second end of the source-side select transistor;

a drain-side select gate line provided to commonly connect gates of the drain-side select transistors;

a source-side select gate line provided to commonly connect gates of the source-side select transistors; and

a control circuit configured to control voltages supplied to the memory blocks,

in performing a read operation of the memory transistor, the control circuit being configured to perform;

supplying a first voltage to a selected word line connected to a selected memory transistor;

supplying a second voltage to a non-selected word line connected to a non-selected memory transistor other than the selected memory transistor, the second voltage being higher than the first voltage;

supplying a third voltage to the bit line;

supplying a fourth voltage lower than the third voltage to, among the source lines, a selected source line connected to a memory string including the selected memory transistor in a selected memory block; and

supplying a fifth voltage substantially the same as the third voltage to, among the source lines, a non-selected source line connected to a non-selected memory string in the selected memory block.

2. The non-volatile semiconductor memory device according to claim 1, wherein

the control circuit supplies the fifth voltage to the source lines in a non-selected memory block other than the selected memory block.

3. The non-volatile semiconductor memory device according to claim 2, wherein

the control circuit comprises:

a first differential amplifier operative to differentially amplify a first reference potential and the potential of the source line and output a first output signal;

a second differential amplifier operative to differentially amplify a second reference potential and the potential of the source line and output a second output signal; and

a first transistor having a first end connected to the source line, the first transistor being provided with the first output signal or the second output signal at its gate.

4. The non-volatile semiconductor memory device according to claim 3, wherein

the control circuit comprises:

a second transistor connected between the source line and the input terminal of the first differential amplifier, the second transistor being switched between a conductive state and a non-conductive state according to a first control signal; and

a third transistor connected between the source line and the input terminal of the second differential amplifier, the third transistor being switched between a conductive state and a non-conductive state according to a second control signal.

5. The non-volatile semiconductor memory device according to claim 1, wherein

the control circuit supplies a sixth voltage to gates of the drain-side select transistor and the source-side select transistor connected to the memory string including the selected memory transistor, and supplies a seventh voltage lower than the sixth voltage to gates of the drain-side select transistor and the source-side select transistor connected to the non-selected memory string.

6. The non-volatile semiconductor memory device according to claim 2, wherein

the control circuit comprises:

a first differential amplifier operative to differentially amplify a first reference potential and the potential of the source line and output a first output signal;

a second differential amplifier operative to differentially amplify a second reference potential and the potential of the source line and output a second output signal;

a first transistor having a first end connected to the source line, the first transistor being provided with the first output signal or the second output signal at its gate; and

a second transistor having a first end connected to the source line, the second transistor being provided with the first output signal or a fixed reference voltage at its gate.

7. The non-volatile semiconductor memory device according to claim 1, wherein

the control circuit comprises:

a first differential amplifier operative to differentially amplify a first reference potential and the potential of the source line and output a first output signal;

a second differential amplifier operative to differentially amplify a second reference potential and the potential of the source line and output a second output signal; and

a first transistor having a first end connected to the source line, the first transistor being provided with the first output signal or the second output signal at its gate.

8. The non-volatile semiconductor memory device according to claim 7, wherein

the control circuit comprises:

a second transistor connected between the source line and the input terminal of the first differential amplifier, the second transistor being switched between a conductive state and a non-conductive state according to a first control signal; and

a third transistor connected between the source line and the input terminal of the second differential amplifier, the third transistor being switched between a conductive state and a non-conductive state according to a second control signal.

9. The non-volatile semiconductor memory device according to claim 7, wherein

the first differential amplifier and the second differential amplifier are shared by the source lines in each of the memory blocks.

10. The non-volatile semiconductor memory device according to claim 1, wherein

the control circuit comprises:

a first differential amplifier operative to differentially amplify a first reference potential and the potential of the source line and output a first output signal;

a second differential amplifier operative to differentially amplify a second reference potential and the potential of the source line and output a second output signal;

a first transistor having a first end connected to the source line, the first transistor being provided with the first output signal or the second output signal at its gate; and

a second transistor a first end connected to the source line, the second transistor being provided with the first output signal or a fixed reference voltage at its gate.

11. The non-volatile semiconductor memory device according to claim 10, wherein

the control circuit comprises:

a second transistor connected between the source line and the input terminal of the first differential amplifier, the second transistor being switched between a conductive state and a non-conductive state according to a first control signal; and

a third transistor connected between the source line and the input terminal of the second differential amplifier, the third transistor being switched between a conductive state and a non-conductive state according to a second control signal.

12. The non-volatile semiconductor memory device according to claim 1, wherein

each of the memory blocks comprises a plurality of sub-blocks,

each of the sub-blocks comprises a plurality of memory strings arranged along one of the drain-side select gate lines and one of the source-side select gate lines, and

each of the source lines is shared by two sub-blocks adjacent to each other.

13. The non-volatile semiconductor memory device according to claim 1, wherein

the source line extends in a second direction intersecting with a first direction in which the plurality of bit lines extends and is commonly connected to the memory strings arranged in the second direction.

14. The non-volatile semiconductor memory device according to claim 13, wherein

one of the source lines is commonly connected to the memory strings adjacent in the first direction.

15. A non-volatile semiconductor memory device comprising:

a memory cell array comprising a plurality of memory blocks;

a plurality of memory strings formed in each of the memory blocks, each memory string including a plurality of memory transistors connected in series, the plurality of memory transistors stacked in a direction perpendicular to a semiconductor substrate;

a drain-side select transistor having a first end connected to a first end portion of each of the memory strings;

a source-side select transistor having a first end connected to a second end portion of each of the memory strings;

a plurality of word lines, each word line being commonly connected to the memory strings disposed in each of the memory blocks;

a plurality of bit lines, each bit line being connected to second ends of the drain-side select transistors in respective memory blocks;

a plurality of source lines each connected to a second end of the source-side select transistor, each of the source lines being provided for one of the memory blocks;

a drain-side select gate line provided to commonly connect the gates of the drain-side select transistors;

a source-side select gate line provided to commonly connect gates of the source-side select transistors; and

a control circuit configured to control voltages supplied to the memory blocks,

in performing a read operation of the memory transistor, the control circuit being configured to perform;

supplying a first voltage to a selected word line connected to a selected memory transistor;

supplying a second voltage to a non-selected word line connected to a non-selected memory transistor other than the selected memory transistor, the second voltage being higher than the first voltage;

supplying a third voltage to the bit line;

supplying a fourth voltage lower than the third voltage to, among the source lines, a source line connected to a selected memory block including the selected memory transistor; and

supplying a fifth voltage substantially the same as the third voltage to, among the source lines, a source line connected to a non-selected memory block other than the selected memory block.

16. The non-volatile semiconductor memory device according to claim 15, wherein

the control circuit supplies the fifth voltage to the source lines in a non-selected memory block other than the selected memory block.

17. The non-volatile semiconductor memory device according to claim 15, wherein

the control circuit supplies a sixth voltage to gates of the drain-side select transistor and the source-side select transistor connected to the memory string including the selected memory transistor

, and supplies a seventh voltage lower than the sixth voltage to gates of the drain-side select transistor and the source-side select transistor connected to the non-selected memory string.

18. A method of controlling a non-volatile semiconductor memory device in a read operation thereof, the non-volatile semiconductor memory device comprising:

a memory cell array comprising a plurality of memory blocks;

a plurality of memory strings formed in each of the memory blocks, each of the memory strings including a plurality of memory transistors connected in series, the plurality of memory transistors stacked in a direction perpendicular to a semiconductor substrate;

a drain-side select transistor having a first end connected to a first end portions of each of the memory strings;

a source-side select transistor having a first end connected to a second end portions of each of the memory strings;

a plurality of word lines, each word line being commonly connected to the memory strings disposed in each of the memory blocks;

a plurality of bit lines extending, each bit lines being connected to second ends of the drain-side select transistors present in respective memory blocks;

a plurality of source lines provided in each of the memory blocks, each of the source lines being connected to a second end of the source-side select transistor;

a drain-side select gate line being provided to commonly connect gates of the drain-side select transistors;

a source-side select gate line being provided to commonly connect gates of the source-side select transistors; and

a control circuit configured to control voltages supplied to the memory blocks,

in the read operation, the method comprising;

supplying a first voltage to a selected word line connected to a selected memory transistor;

supplying a second voltage to a non-selected word line connected to a non-selected memory transistor other than the selected memory transistor, the second voltage being higher than the first voltage;

supplying a third voltage to the bit line;

supplying a fourth voltage lower than the third voltage to, among the source lines, a selected source line connected to a memory string including the selected memory transistor in a selected memory block; and

supplying a fifth voltage substantially the same as the third voltage to, among the source lines, a non-selected source line connected to a non-selected memory string in the selected memory block.

19. The method according to claim 18, further comprising supplying the fifth voltage to the source lines in a non-selected memory block other than the selected memory block.

20. The method according to claim 18, further comprising:

supplying a sixth voltage to gates of the drain-side select transistor and the source-side select transistor connected to the memory string including the selected memory transistor to render the drain-side select transistor and the source-side select transistor conductive; and

supplying a seventh voltage lower than the sixth voltage to gates of the drain-side select transistor and the source-side select transistor connected to the non-selected memory string to maintain the drain-side select transistor and the source-side select transistor in a non-conductive state.