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FABRICATION METHOD OF TRENCHED POWER SEMICONDUCTOR DEVICE WITH SOURCE TRENCH

  • US 20120322217A1
  • Filed: 05/12/2012
  • Published: 12/20/2012
  • Est. Priority Date: 06/20/2011
  • Status: Active Grant
First Claim
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1. a fabrication method of a trenched power semiconductor device with a source trench, comprising the steps of:

  • providing a base;

    forming at least two gate trenches in the base;

    forming a first dielectric layer to line the inner surfaces of the gate trenches;

    forming a first polysilicon structure in the gate trenches lining with the first dielectric layer;

    forming at least a source trench between the two neighboring gate trenches;

    forming a second dielectric layer to line the inner surfaces of the source trench;

    forming a second polysilicon structure in a lower portion of the source trench lining with the second dielectric layer;

    forming a body region between the gate trenches, wherein the depth of the source trench is greater than the depth of the body region;

    forming a source region between the gate trenches;

    removing a portion of the second dielectric layer to expose the source region and the body region; and

    filling a conductive structure in the source trench for electrically connecting the second polysilicon structure, the body region, and the source region.

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