FABRICATION METHOD OF TRENCHED POWER SEMICONDUCTOR DEVICE WITH SOURCE TRENCH

• US 20120322217A1
• Filed: 05/12/2012
• Published: 12/20/2012
• Est. Priority Date: 06/20/2011
• Status: Active Grant

• Current Assignee: Super Group Semiconductor Co., Ltd.
• Original Assignee: Great Power Semiconductor Corp.
• Inventors: YEH, CHUN YING, HSU, HSIU WEN
• Granted Patent: US 8,846,469 B2
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A fabrication method of a trenched power semiconductor device with source trench is provided. Firstly, at least two gate trenches are formed in a base. Then, a dielectric layer and a polysilicon structure are sequentially formed in the gate trench. Afterward, at least a source trench is formed between the neighboring gate trenches. Next, the dielectric layer and a second polysilicon structure are sequentially formed in the source trench. The second polysilicon structure is located in a lower portion of the source trench. Then, the exposed portion of the dielectric layer in the source trench is removed to expose a source region and a body region. Finally, a conductive structure is filled into the source trench to electrically connect the second polysilicon structure, the body region, and the source region.

Claims

1. a fabrication method of a trenched power semiconductor device with a source trench, comprising the steps of:

providing a base;

forming at least two gate trenches in the base;

forming a first dielectric layer to line the inner surfaces of the gate trenches;

forming a first polysilicon structure in the gate trenches lining with the first dielectric layer;

forming at least a source trench between the two neighboring gate trenches;

forming a second dielectric layer to line the inner surfaces of the source trench;

forming a second polysilicon structure in a lower portion of the source trench lining with the second dielectric layer;

forming a body region between the gate trenches, wherein the depth of the source trench is greater than the depth of the body region;

forming a source region between the gate trenches;

removing a portion of the second dielectric layer to expose the source region and the body region; and

filling a conductive structure in the source trench for electrically connecting the second polysilicon structure, the body region, and the source region.

2. The fabrication method of a trenched power semiconductor device with a source trench of claim 1, wherein a depth of the source trench extending into the base is greater than the depth of the gate trench and an upper surface of the second polysilicon structure is placed above a bottom surface of the body region.

3. The fabrication method of a trenched power semiconductor device with a source trench of claim 1, further comprising the step of forming a heavily doped region in the body region.

4. The fabrication method of a trenched power semiconductor device with a source trench of claim 1, further comprising the step of forming an interlayer dielectric structure on the first polysilicon structure to define the source trench.

5. The fabrication method of a trenched power semiconductor device with a source trench of claim 4, further comprising the step of forming a heavily doped region by using the interlayer dielectric structure as an implantation mask.

6. The fabrication method of a trenched power semiconductor device with a source trench of claim 5, wherein the step of forming the heavily doped region comprises:

reducing a line width of the interlayer dielectric structure through etching to expose the body region therebelow;

etching the body region to form a contact window by using the etched interlayer dielectric structure as an etching mask; and

forming the heavily doped region in a bottom region below the contact window.

7. The fabrication method of a trenched power semiconductor device with a source trench of claim 6, wherein the step of reducing the line width of the interlayer dielectric structure is carried out by using isotropic etching technique.

8. The fabrication method of a trenched power semiconductor device with a source trench of claim 7, wherein the step of reducing the line width of the interlayer dielectric structure and the step of removing the portion of the second dielectric layer are carried out simultaneously.

9. The fabrication method of a trenched power semiconductor device with a source trench of claim 6, wherein a portion of the second polysilicon structure is removed in the step of etching the body region to form the contact window.

10. The fabrication method of a trenched power semiconductor device with a source trench of claim 5, wherein after the step of forming the source trench penetrating the heavily doped region, a portion of the heavily doped region is left adjacent to a sidewall of the source trench.

11. The fabrication method of a trenched power semiconductor device with a source trench of claim 4, after the step of forming the source trench, further comprising the step of forming a heavily doped region adjacent to a sidewall of the source trench by using tilted ion implanting technique.

12. The fabrication method of a trenched power semiconductor device with a source trench of claim 4, wherein the step of forming the source trench comprises:

forming a spacer on a side surface of the interlayer dielectric structure; and

etching the exposed body region to form the source trench.

13. The fabrication method of a trenched power semiconductor device with a source trench of claim 12, prior to the formation of the spacer, further comprising the step of forming a heavily doped region in the body region by using the interlayer dielectric structure as an implantation mask.

14. The fabrication method of a trenched power semiconductor device with a source trench of claim 12, wherein the spacer is removed in the step of removing the portion of the second dielectric layer to expose the source region and the body region.

15. The fabrication method of a trenched power semiconductor device with a source trench of claim 1, wherein the step of forming the source trench is prior to the step of forming the body region.

16. The fabrication method of a trenched power semiconductor device with a source trench of claim 1, wherein the step of forming the body region is prior to the step of forming the source trench.