ELECTRONIC ENDOSCOPIC APPARATUS
First Claim
1. An electronic endoscopic apparatus comprising:
- an imaging device that is installed on a scope distal portion and captures an image based on an imaging clock;
an image processor portion that performs image processing on the image captured by the imaging device and displays the corresponding image on a monitor based on a display clock;
a scope cable portion that transmits data between the scope distal portion and the image processor portion;
a clock oscillator that generates a master clock; and
a multiplying/dividing circuit that multiplies and/or divides the master clock by (natural number/natural number) and generates a transmission clock whose frequency is lower than that of the imaging clock and is (natural number) times the frequency of a vertical synchronization signal.
1 Assignment
0 Petitions
Accused Products
Abstract
An imaging device is installed on a scope distal portion, and captures an image based on an imaging clock. An image processor portion performs image processing on the image captured by the imaging device, and displays the corresponding image based on a display clock on a monitor. A scope cable portion transmits data between the scope distal portion and the image processor portion. A clock oscillator generates a master clock. A first multiplying/dividing circuit multiplies and/or divides the master clock by (natural number/natural number), and generates a transmission clock whose frequency is lower than that of the imaging clock and is (natural number) times the frequency of a vertical synchronization signal.
15 Citations
15 Claims
-
1. An electronic endoscopic apparatus comprising:
-
an imaging device that is installed on a scope distal portion and captures an image based on an imaging clock; an image processor portion that performs image processing on the image captured by the imaging device and displays the corresponding image on a monitor based on a display clock; a scope cable portion that transmits data between the scope distal portion and the image processor portion; a clock oscillator that generates a master clock; and a multiplying/dividing circuit that multiplies and/or divides the master clock by (natural number/natural number) and generates a transmission clock whose frequency is lower than that of the imaging clock and is (natural number) times the frequency of a vertical synchronization signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
-
Specification